Intel Cyclone 10 GX User Manual page 176

The rate match FIFO can insert as many pairs of skip patterns into a cluster
necessary to avoid the rate match FIFO from under running. The 10-bit skip
pattern can appear on the MSByte, the LSByte, or both, of the 20-bit word.
Figure 101. Rate Match FIFO Deletion with Four Skip Patterns Required for Deletion
/K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern.
tx_parallel_data[19:10]
rx_parallel_data[19:0]
rx_parallel_data[9:0]
In the following figure, /K28.5/ is the control pattern and neutral disparity /K28.0/
is the skip pattern. The first skip cluster has a /K28.5/ control pattern in the
LSByte and /K28.0/ skip pattern in the MSByte of a clock cycle. The rate match
FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip
pattern insertion requirement.
Figure 102. Rate Match FIFO Insertion with Four Skip Patterns Required for Insertion
tx_parallel_data[19:10]
rx_parallel_data[19:0]
rx_parallel_data[9:0]
The following figure shows the deletion of the 20-bit word D7D8.
Figure 103. Rate Match FIFO Becoming Full After Receiving the 20-Bit Word D5D6
tx_parallel_data[19:0]
tx_parallel_data[9:0]
rx_parallel_data[19:10]
rx_parallel_data[9:0]
rx_std_rmfifo_full
The following figure shows the insertion of two skip symbols.
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Intel Cyclone 10 GX Transceiver PHY User Guide
176
Dx.y
tx_parallel_data[9:0] Dx.y
Dx.y
Dx.y
First Skip Cluster
Dx.y K28.0
tx_parallel_data[9:0] Dx.y K28.5
Dx.y K28.0
Dx.y K28.5
D2
D1
D2
D1
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
First Skip Cluster
K28.0 Dx.y K28.5
K28.5 K28.0 Dx.y
K28.0 Dx.y K28.5
K28.5 K28.0 Dx.y
Second Skip Cluster
Dx.y K28.5 K28.0
Dx.y Dx.y K28.0
K28.0 K28.0 Dx.y
K28.0 K28.0 Dx.y
D4 D6
D3 D5
D4 D6
D3 D5
UG-20070 | 2018.09.24
Two Pairs of Skip
Second Skip Cluster Patterns Deleted
K28.0 K28.0 Dx.y
K28.0 K28.0 Dx.y
Dx.y
Dx.y
K28.0
K28.0
K28.5 K28.0 K28.0
Dx.y K28.0 K28.0
D8 D10
D7 D9
D10 D12
D9 D11
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D12
D11
xx
xx