Fpll Ip Parameter Core Settings For Pipe - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Parameter
Enable TX polarity inversion
Enable port
tx_polinv
Enable RX bit reversal
Enable
rx_std_bitrev_ena
Enable RX byte reversal
Enable
rx_std_byterev_ena
Enable RX polarity inversion
Enable port
rx_polinv
Enable
rx_std_signaldetect
PCIe Ports
Enable PCIe dynamic datarate switch ports
Enable PCIe
pipe_hclk_in
ports
Enable PCIe electrical idle control and status ports
Enable PCIe
pipe_rx_polarity
Dynamic reconfiguration
Enable dynamic reconfiguration
Note: The signals in the left-most column are automatically mapped to a subset of a 128-bit
tx_parallel_data
Related Information
• Using the Cyclone 10 GX Transceiver Native PHY IP Core
• Bit Mappings When the Simplified Interface Is Disabled

2.7.6. fPLL IP Parameter Core Settings for PIPE

Table 124. Parameter Settings for Cyclone 10 GX fPLL IP core in PIPE Gen1, Gen2 modes
This section contains the recommended parameter values for this protocol. Refer to Using the Cyclone 10 GX
Transceiver Native PHY IP Core for the full range of parameter values.
Parameter
PLL
General
fPLL mode
Protocol Mode
Message level for rule violation
Number of PLL reference clocks
Selected reference clock source
Enable fractional mode
Send Feedback
port
port
port
and
pipe_hclk_out
port
word when the Simplified Interface is enabled.
Gen1 PIPE
Transceiver
PCIe Gen 1
Error
1
0
Disable
Gen1 PIPE
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Off
Enabled
Enabled
Enabled
Disabled
on page 26
on page 143
Transceiver
PCIe Gen 2
Error
1
0
Disable
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
Gen2 PIPE
Off
Off
Off
Off
Off
Off
Off
Off
Optional
Enabled
Enabled
Enabled
Enabled
Disabled
Gen2 PIPE
continued...
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