Intel Cyclone 10 GX User Manual page 265

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Signal Name
rx_cal_busy[<n> -1:0]
rx_is_lockedtodata[<n
>-1:0]
tx_manual[<n>-1:0]
rx_manual[<n> -1:0]
clock
reset
tx_digitalreset[<n>-1
:0]
Send Feedback
Direction Clock Domain
Input Asynchronous
Input Synchronous to CDR
Input Asynchronous
Input Asynchronous
Input N/A
Input Asynchronous
Output Synchronous to the
Transceiver PHY Reset
Controller input clock.
Description
This is calibration status signal from the Transceiver
PHY IP core. When asserted, the initial calibration is
active. When deasserted, calibration has completed. It
will not be asserted if you manually re-trigger the
calibration IP. This signal gates the RX reset sequence.
The width of this signals depends on the number of RX
channels.
Provides the
rx_is_lockedtodata
RX CDR. When asserted, indicates that a particular RX
CDR is ready to receive input data. If you do not
choose separate controls for the RX channels, these
inputs are ANDed together internally to provide a
single status signal.
This optional signal places
tx_digitalreset
controller under automatic or manual control. When
asserted, the associated
tx_digitalreset
logic does not automatically respond to deassertion of
the signal. However, the initial
pll_locked
sequence still requires a one-time
tx_digitalreset
rising edge on before proceeding. When
pll_locked
deasserted, the associated
tx_digitalreset
controller automatically begins its reset sequence
whenever the selected
pll_locked
deasserted.
This optional signal places
rx_digitalreset
controller under automatic or manual control. In
manual mode, the
rx_digitalreset
not respond to the assertion or deassertion of the
signal. The
rx_is_lockedtodata
controller asserts
rx_digitalreset
the signal is asserted.
rx_is_lockedtodata
A free running system clock input to the Transceiver
PHY Reset Controller from which all internal logic is
driven. If a free running clock is not available, hold
reset until the system clock is stable.
Asynchronous reset input to the Transceiver PHY Reset
Controller. When asserted, all configured reset outputs
are asserted. Holding the reset input signal asserted
holds all other reset outputs asserted. An option is
available to synchronize with the system clock. In
synchronous mode, the reset signal needs to stay
asserted for at least (2) clock cycles by default.
Digital reset for TX channels. The width of this signal
depends on the number of TX channels. This signal is
asserted when any of the following conditions is true:
•
is asserted
reset
•
is asserted
pll_powerdown
•
is asserted
pll_cal_busy
•
is asserted
tx_cal_busy
•
PLL has not reached the initial lock (
deasserted)
•
is deasserted and
pll_locked
deasserted
When all of these conditions are false, the reset
counter begins its countdown for deassertion of
.
tx_digitalreset
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
status from each
controller
signal is
logic
controller does
when
rx_ready
pll_locked
is
tx_manual
continued...
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