Intel Cyclone 10 GX User Manual page 78

Figure 25. State Flow of the RX FIFO Deskew
Each lane's
deskew is completed. After frame lock is achieved (indicated by the assertion of
rx_enh_frame_lock
written into the RX FIFO after the first alignment word (SYNC word) is found on that
channel. Accordingly, the RX FIFO partially empty flag (
that channel is asserted. The state machine monitors the
rx_enh_fifo_pfull
from all channels deassert before any channels
implies the SYNC word has been found on all lanes of the link, the MAC layer can start
reading from all the RX FIFO by asserting
Otherwise, if the
rx_enh_fifo_pempty
to flush the RX FIFO by asserting
repeating the soft deskew process.
The following figure shows one RX deskew scenario. In this scenario, all of the RX
FIFO partially empty lanes are deasserted while the pfull lanes are still deasserted.
This indicates the deskew is successful and the FPGA fabric starts reading data from
the RX FIFO.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
78
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Exit from
rx_digitalreset
Deassert all Lane's rx_enh_fifo_rd_en
All Lane's
rx_enh_fifo_pempty
Deasserted?
yes
All Lane's
rx_enh_fifo_pfull
Deasserted?
yes
RX FIFO Deskew
Completed
rx_enh_fifo_rd_en
; this signal is not shown in the above state flow), data is
signals of all channels. If the
rx_enh_fifo_pfull
signals deassertion on all channels, the state machine needs
rx_enh_fifo_align_clr
no
Assert rx_enh_fifo_align_clr for at
least 4 rx_coreclkin Cycles
no
should remain deasserted before the RX FIFO
rx_enh_fifo_pempty
rx_enh_fifo_pempty
rx_enh_fifo_pempty
rx_enh_fifo_pfull
rx_enh_fifo_rd_en
signal of any channel asserts high before the
UG-20070 | 2018.09.24
) of
and
signals
assert, which
simultaneously.
high for 4 cycles and
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