Intel Cyclone 10 GX User Manual page 273

5. Cyclone 10 GX Transceiver PHY Architecture
UG-20070 | 2018.09.24
Figure 168. Serializer Block
The serializer block sends out the least significant bit (LSB) of the input data first.
LSB
D0
5.1.1.2. Transmitter Buffer
The transmitter buffer includes the following circuitry:
• High Speed Differential I/O
• Programmable differential output voltage (V
— Main tap
• Programmable four-tap pre-emphasis circuitry
— Two pre-cursor taps
— Two post-cursor taps
• Power distribution network (PDN) induced inter-symbol interference (ISI)
compensation
• Internal termination circuitry
• Receiver detect capability to support the PCI Express configuration
Send Feedback
D1 D2
Serial
Data
Dn
Serializer
Serial Parallel
Clock Clock
)
OD
®
Intel Cyclone
Dn
Parallel
D2
Data
D1
D0
®
10 GX Transceiver PHY User Guide
273