Intel Cyclone 10 GX User Manual page 164

2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS
In the Parameter Editor, use the following settings to enable low latency:
1. Select the Enable 'Enhanced PCS' low latency mode option.
2. Select one of the following gear ratios:
Single-width mode: 32:32, 40:40, 64:64, 66:40, 66:64, or 64:32
Double-width mode: 40:40, 64:64, or 66:64
3. Select Phase_compensation in the TX and RX FIFO mode list.
4. If you need the Scrambler and Descrambler features, enable Block Synchronize
and use the 66:32, 66:40, or 66:64 gear ratio.
2.9.1.4. Enhanced PCS FIFO Operation
Phase Compensation Mode
Phase compensation mode ensures correct data transfer between the core clock and
parallel clock domains. The read and write sides of the TX Core or RX Core FIFO must
be driven by the same clock frequency. The depth of the TX or RX FIFO is constant in
this mode. Therefore, the TX Core or RX Core FIFO flag status can be ignored. You can
tie
tx_fifo_wr_en
Basic Mode
Basic mode allows you to drive the write and read side of a FIFO with different clock
frequencies.
the lane data rate divided by 66. The frequency range for
rx_coreclkin
recommends that
the FIFO flag to control write and read operations.
For TX FIFO, assert
This can be done with the following example assignment:
assign tx_enh_data_valid = ~tx_fifo_pfull;
Figure 79. TX FIFO Basic Mode Operation
tx_clkout (read side)
tx_coreclk (write side)
tx_parallel_data[63:0]
tx_digitalreset
tx_enh_datavalid
tx_fifo_pfull
For RX FIFO, assert
This can be done with the following example assignment:
assign rx_enh_read_en = ~rx_fifo_pempty;
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
164
or
rx_data_valid
or
tx_coreclkin
is (data rate/32) to (data rate/66). For best results, Intel
tx_coreclkin
tx_enh_data_valid
64' d 0 64' d 1 64' d 2
tx_fifo_pempty
tx_fifo_full
rx_enh_read_en
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
to 1.
must have a minimum frequency of
rx_coreclkin
or be set to (data rate/32). Monitor
rx_coreclkin
with the
tx_fifo_pfull
64' d 3 64' d 4 64' d 5 64' d 6
with the
rx_fifo_pempty
UG-20070 | 2018.09.24
or
tx_coreclkin
signal going low.
64' d 7 64' d 8 64' d 9 64'ha
signal going low.
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