Table Of Contents - Intel Cyclone 10 GX User Manual

Contents
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1. Intel Cyclone 10 GX Transceiver PHY Overview ......................................................... 7
1.1. Device Transceiver Layout......................................................................................8
1.1.1. Intel Cyclone 10 GX Device Transceiver Layout.............................................. 8
1.1.2. Intel Cyclone 10 GX Device Package Details ................................................10
1.2. Transceiver PHY Architecture Overview.................................................................. 10
1.2.1. Transceiver Bank Architecture....................................................................10
1.2.2. PHY Layer Transceiver Components........................................................... 11
1.2.3. Transceiver Phase-Locked Loops................................................................ 13
1.2.4. Clock Generation Block (CGB)...................................................................14
1.3. Calibration.......................................................................................................... 14
1.4. Intel Cyclone 10 GX Transceiver PHY Overview Revision History................................. 15
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers....................................... 16
2.1. Transceiver Design IP Blocks................................................................................. 16
2.2. Transceiver Design Flow........................................................................................17
2.2.1. Select and Instantiate the PHY IP Core........................................................17
2.2.2. Configure the PHY IP Core.........................................................................19
2.2.3. Generate the PHY IP Core......................................................................... 19
2.2.4. Select the PLL IP Core.............................................................................. 19
2.2.5. Configure the PLL IP Core........................................................................ 20
2.2.6. Generate the PLL IP Core ......................................................................... 21
2.2.7. Reset Controller ...................................................................................... 21
2.2.8. Create Reconfiguration Logic..................................................................... 21
2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller........................... 22
2.2.10. Connect Datapath ................................................................................ 22
2.2.11. Make Analog Parameter Settings ............................................................. 22
2.2.12. Compile the Design................................................................................ 22
2.2.13. Verify Design Functionality...................................................................... 22
2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support......................................... 24
2.4. Using the Cyclone 10 GX Transceiver Native PHY IP Core...........................................26
2.4.1. Presets................................................................................................... 28
2.4.2. General and Datapath Parameters ............................................................. 28
2.4.3. PMA Parameters......................................................................................31
2.4.4. Enhanced PCS Parameters ........................................................................34
2.4.5. Standard PCS Parameters........................................................................ 41
2.4.6. PCS Direct ............................................................................................ 45
2.4.7. Dynamic Reconfiguration Parameters.......................................................... 45
2.4.8. PMA Ports.............................................................................................. 50
2.4.9. Enhanced PCS Ports................................................................................ 53
2.4.10. Standard PCS Ports................................................................................ 62
2.4.11. IP Core File Locations............................................................................. 67
2.4.12. Unused Transceiver Channels...................................................................69
2.5. Interlaken..........................................................................................................70
2.5.1. Metaframe Format and Framing Layer Control Word.....................................71
2.5.2. Interlaken Configuration Clocking and Bonding............................................73
2.5.3. How to Implement Interlaken in Cyclone 10 GX Transceivers......................... 79
2.5.4. Native PHY IP Parameter Settings for Interlaken..........................................82
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Intel Cyclone 10 GX Transceiver PHY User Guide
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