Intel Cyclone 10 GX User Manual
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Intel Cyclone 10 GX User Manual

Intel Cyclone 10 GX User Manual

Xcvr toolkit reference design
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Cyclone 10 GX XCVR Toolkit Reference Design
v17.1.1 User Guide
Date: January 2018
Revision: 1.0
©2017 Intel Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, INTEL, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Intel Corporation and registered in the U.S. Patent and Trademark
Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective
holders as described at www.altera.com/common/legal.html. Intel warrants performance of its semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at
any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.

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Summary of Contents for Intel Cyclone 10 GX

  • Page 1 Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel.

  • Page 2: Table Of Contents

    Table of Contents Introduction ................................3 Requirement ................................3 Theory of Operation..............................3 How to Setup the Development Kits for XCVR Loopback Test ................4 How to Reconstruct and Run the Reference Design ....................5 Hardware setup: ..............................5 XCVR Channel Loopback Test Run Procedure : ....................8 Conclusion ................................

  • Page 3: Introduction

    Figure 1 shows the high-level modules in the reference design as well as the interfaces among the modules. The Cyclone 10 GX XCVR NativePHY IP is used to generate one 1.25Gbps XCVR duplex channel. The XCVR Reset Controller IP is used to perform the reset to the XCVR channel and ATXPLL. The ATXPLL IP serves as XCVR PLL...

  • Page 4: How To Setup The Development Kits For Xcvr Loopback Test

    Follow these steps to setup the hardware to run the reference design: 1. Connect the FMC loopback card to the FMC port on the Cyclone 10 GX Development Kit Board 2. Ensure Switch 9 (S9) settings of the Development Kit Board is set to “on” position 3.

  • Page 5: How To Reconstruct And Run The Reference Design

    How to Reconstruct and Run the Reference Design Hardware setup: 1. Follow the instruction in the Design Store to prepare the design template and load the design into your Quartus software 2. Perform full compilation with the Quartus design 3. Carry out following steps to reduce the JTAG frequency from default 24MHz to 16MHz to avoid JTAG connection issue a.
  • Page 6 Only execute step 4 if your C10 GX Development Kit Board belongs to 1 prototype build with board serial number within 0000001-0000030 else skip to step 5. For 1 prototype board, by default after power up the development kit board, the programmable clock generator (Si5332) used for the transceiver channel in this design is disabled.
  • Page 7 e. After successful configuration, the Clock Controller GUI should look like Figure 5 Figure 5. Clock Controller GUI for Si5332 after Successful Configuration f. Close the Clock Controller application g. Note that you would need to reconfigure the Si5332 using step 4(b) -> 4(f) each time the Development Kit Board is power-cycled 5.

  • Page 8: Xcvr Channel Loopback Test Run Procedure

    XCVR Channel Loopback Test Run Procedure : 1. Launch Transceiver toolkit 2. In Quartus software, goto Tools -> System Debugging Tools -> Transceiver Toolkit 3. Click “Load Design” and select the programmed SOF file. 4. Toolkit should initialize one XCVR duplex channel as shown in Figure 6. Figure 6.
  • Page 9 b. Click “Start” button and monitor CDR lock status, number of bits tested and Bit Error Rate (BER) c. Test is considered pass when CDR is locked and BER result is zero d. Test run is continuous. Click “Stop” and then click “Reset” to stop test. 7.
  • Page 10 8. Procedure to test External On Board Loopback with (FMC Loopback Card removed from board) a. Power down Development Kit Board b. Remove FMC Loopback Card from Development Kit Board and power on the board c. Follow hardware setup guide to reduce JTAG clock and configure Clock Controller GUI if necessary d.

  • Page 11: Conclusion

    This reference design provides user a quick start guide to perform XCVR channel hardware test verification in transceiver toolkit by using simple NativePHY IP design. References • Intel Cyclone 10 GX Transceiver PHY User Guide https://www.altera.com/documentation/hki1486507600636.html • Intel Cyclone 10 GX Development Kit Board Website https://www.altera.com/products/boards_and_kits/dev-kits/altera/cyclone-10-gx-development-kit.html...

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