Transceiver Phy Reset Controller Resource Utilization; Using A User-Coded Reset Controller - Intel Cyclone 10 GX User Manual

4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
Usage Examples for
•
If a single channel can switch between three TX PLLs, the
indicates which one of the selected three TX PLL's
communicate the PLL lock status to the TX reset sequence. In this case, to select
the 3-bits wide
• If three channels are instantiated with three TX PLLs and with a separate TX reset
sequence per channel, the
In this case,
represents channel 1, and
channel, a separate
• If three channels are instantiated with three TX PLLs and with a single TX reset
sequence for all three channels, then
case, the same
channels.
•
If one channel is instantiated with one TX PLL,
Connect
• If three channels are instantiated with only one TX PLL and with a separate TX
reset sequence per channel, the
pll_select

4.4.4. Transceiver PHY Reset Controller Resource Utilization

This section describes the estimated device resource utilization for two configurations
of the transceiver PHY reset controller. The exact resource count varies by Quartus
Prime version number, as well as by optimization options.
Table 161. Reset Controller Resource Utilization
Single transceiver channel
Four transceiver channels, shared TX reset, separate RX resets

4.5. Using a User-Coded Reset Controller

You can design your own user-coded reset controller instead of using Transceiver PHY
Reset Controller. Your user-coded reset controller must provide the following
functionality for the recommended reset sequence:
• A clock signal input for your reset logic
• Holds the transceiver channels in reset by asserting the appropriate reset control
signals
•
Checks the PLL status (for example, checks the status of
pll_cal_busy
Note: You must ensure a stable reference clock is present at the PLL transmitter before
releasing
Send Feedback
pll_select
pll_locked
pll_select
pll_select [1:0]
pll_select[5:4]
pll_locked
pll_locked
to logic 0.
pll_select
should be set to 0 since there is only one TX PLL available.
Configuration
)
.
pll_powerdown
pll_locked
port, the
pll_select
field is 6-bits wide (2-bits per channel).
represents channel 0,
represents channel 2. For each
signal indicates the PLL lock status.
field is 2-bits wide. In this
pll_select
signal indicates the PLL lock status for all three
pll_select
field is 3-bits wide. In this case,
pll_select
Combination ALUTs
approximately 50
approximately 100
®
Intel Cyclone
signal
pll_select
signal is used to
port is 2-bits wide.
pll_select[3:2]
field is 1-bit wide.
Logic Registers
approximately 50
approximately 150
and
pll_locked
®
10 GX Transceiver PHY User Guide
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