Intel Cyclone 10 GX User Manual page 256

4.3.2.1.2. Resetting the Receiver During Device Operation
The numbers in this list correspond to the numbers in the following figure.
1. Assert
2. Wait for
rx_analogreset
completed the reset request for assertion.
a. Deassert
3. Wait for
rx_analogreset
completed the reset request for deassertion.
4. The
rx_is_lockedtodata
5. Ensure
deasserting
Figure 158. Receiver Reset Sequence During Device Operation
4.3.2.1.3. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment
Model
The numbers in this list correspond to the numbers in the following figure.
1. Assert
pll_cal_busy
2. Wait for
tx_analogreset
completed the reset request for assertion.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
256
and
rx_analogreset
rx_analogreset_ack
.
rx_analogreset_ack
rx_analogreset
rx_analogreset_ack
.
rx_analogreset_ack
signal goes high after the CDR acquires lock.
rx_is_lockedtodata
rx_digitalreset
Device Power Up
rx_cal_busy
rx_analogreset
rx_analogreset_ack
rx_is_lockedtodata
rx_digitalreset
,
tx_analogreset pll_powerdown
and
tx_cal_busy
tx_analogreset_ack
.
tx_analogreset_ack
while
rx_digitalreset
to go high, to ensure successful assertion of
goes high when TRS has successfully
.
to go low, to ensure successful deassertion of
goes low when TRS has successfully
is asserted for t (minimum of 4 μs) before
LTD
.
1 2 3 4
, and
tx_digitalreset
are low.
to go high, to ensure successful assertion of
goes high when TRS has successfully
4. Resetting Transceiver Channels
UG-20070 | 2018.09.24
is low.
rx_cal_busy
t min 4 μs
LTD
5
, while
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