Intel Cyclone 10 GX User Manual page 117

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
2.6.3.5.1. Clock and Reset Signals
Table 109. Clock and Reset Signals
Signal Name
Clock signals
csr_clk
xgmii_tx_coreclkin
xgmii_rx_coreclkin
tx_serial_clk
rx_cdr_refclk_1
rx_pma_clkout
Reset signals
reset
tx_analogreset
tx_digitalreset
rx_analogreset
rx_digitalreset
Send Feedback
Direction Width
Input 1
Input 1
Input 1
Input 1
Input 1
Output 1
Input 1
Input 1
Input 1
Input 1
Input 1
Description
Clock for the Avalon-MM control and status
interface. Intel recommends 125 – 156.25 MHz for
this clock.
XGMII TX clock. Provides timing reference and
312.5 MHz for 10M/100M/1G/2.5G/5G/10G
(USXGMII) mode. Synchronous to
with zero ppm.
tx_serial_clk
XGMII RX clock. Provides timing reference and
312.5 MHz for 10M/100M/1G/2.5G/5G/10G
(USXGMII) mode.
Serial clock from transceiver PLLs.
• 10M/100M/1G/2.5G/5G/10G (USXGMII) mode:
Provide 5156.25 MHz to this input port.
RX CDR reference clock for 10GbE. The frequency
of this clock can be either 322.265625 MHz or
644.53125 MHz, as specified by the Reference
clock frequency for 10 GbE (MHz) parameter
setting.
Recovered clock from CDR, operates at the
following frequency:
• 10GbE: 322.265625 MHz
Active-high global reset. Assert this signal to
trigger an asynchronous global reset.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the analog block on the TX
path.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the TX
path.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the receiver CDR.
Connect this signal to the Transceiver PHY Reset
Controller IP core. When asserted, triggers an
asynchronous reset to the digital logic on the RX
path.
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Intel Cyclone 10 GX Transceiver PHY User Guide
117