Intel Cyclone 10 GX User Manual page 32

Table 7. TX PLL Options
Parameter
TX local clock division
factor
Number of TX PLL
clock inputs per
channel
Initial TX PLL clock
input selection
Table 8. TX PMA Optional Ports
Parameter
Enable
tx_pma_analog_reset_ack
port
Enable tx_pma_clkout port
Enable tx_pma_div_clkout
port
tx_pma_div_clkout division
factor
Enable
tx_pma_iqtxrx_clkout port
Enable tx_pma_elecidle
port
Enable rx_seriallpbken port
Table 9. RX CDR Options
Parameter
Number of CDR reference
clocks
(10)
This clock should not be used to clock the FPGA - transceivers interface. This clock may be
used as a reference clock to an external clock cleaner.
(11)
The default value is Disabled.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
32
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Value
1, 2, 4, 8 Specifies the value of the divider available in the transceiver
channels to divide the TX PLL output clock to generate the correct
frequencies for the parallel and serial clocks.
1, 2, 3 , 4 Specifies the number of TX PLL clock inputs per channel. Use this
parameter when you plan to dynamically switch between TX PLL
clock sources. Up to four input sources are possible.
0 to <number of TX Specifies the initially selected TX PLL clock input. This parameter
PLL clock inputs> -1 is necessary when you plan to switch between multiple TX PLL
clock inputs.
Value
On/Off
Enables the optional
This port should not be used for register mode data transfers.
On/Off
Enables the optional
speed parallel clock from the TX PMA. The source of this clock is
the serializer. It is driven by the PCS/PMA interface block.
On/Off Enables the optional
clock is generated by the serializer. You can use this to drive core
logic, to drive the FPGA - transceivers interface.
If you select a tx_pma_div_clkout division factor of 1 or 2,
this clock output is derived from the PMA parallel clock. If you
select a tx_pma_div_clkout division factor of 33, 40, or 66,
this clock is derived from the PMA high serial clock. This clock is
commonly used when the interface to the TX FIFO runs at a
different rate than the PMA parallel clock frequency, such as 66:40
applications.
Disabled, 1, 2,
Selects the division factor for the
33, 40, 66
clock when enabled.
On/Off
Enables the optional
clock can be used to cascade the TX PMA output clock to the input
of a PLL.
On/Off
Enables the
the transmitter is forced into an electrical idle condition. This port
has no effect when the transceiver is configured for PCI Express.
On/Off
Enables the optional
assertion of this signal enables the TX to RX serial loopback path
within the transceiver. This is an asynchronous input signal.
Value
1 - 5 Specifies the number of CDR reference clocks. Up to 5 sources are
possible.
The default value is 1.
Description
Description
tx_pma_analog_reset_ack
output clock. This is the low
tx_pma_clkout
tx_pma_div_clkout
tx_pma_div_clkout
(11)
tx_pma_iqtxrx_clkout
port. When you assert this port,
tx_pma_elecidle
control input port. The
rx_seriallpbken
Description
UG-20070 | 2018.09.24
output port.
(10)
output clock. This
output
output clock. This
continued...
Send Feedback