Intel Cyclone 10 GX User Manual page 142

Port
pipe_sw_done[1:0]
rx_parallel_data[15:0]
or
[7:0]
or
rx_datak[1:0] [0]
pipe_rx_valid[(N-1):0]
pipe_phy_status[(N-1):
0]
pipe_rx_elecidle[(N-1):
0]
pipe_rx_status[(3N-1):
0]
pipe_sw[1:0]
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
142
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Direction Clock Domain
In N/A
PIPE Output to PHY - MAC Layer
Out
rx_coreclkin
Out
rx_coreclkin
Out
rx_coreclkin
Out
rx_coreclkin
Out Asynchronous
Out
rx_coreclkin
Out N/A
UG-20070 | 2018.09.24
Description
Signal from the Master clock generation
buffer, indicating that the rate switch has
completed. Use this signal for bonding mode
only (x2 and x4).
For non-bonded applications (x1), this signal
is internally connected to the local CGB.
The RX parallel data driven to the MAC.
For Gen1 this can be 8 or 16 bits. For Gen2
this is 16 bits only. Refer to Bit Mappings
When the Simplified Interface is Disabled for
more details.
The data and control indicator.
For Gen1 or Gen2, when 0, indicates that
is data, when 1,
rx_parallel_data
indicates that
rx_parallel_data
control.
Asserted when RX data and control are valid.
Signal used to communicate completion of
several PHY requests.
Active High
When asserted, the receiver has detected an
electrical idle.
Active High
Signal encodes receive status and error
codes for the receive data stream and
receiver detection. The following encodings
are defined:
3'b000 - Receive data OK
3'b001 - 1 SKP added
3'b010 - 1 SKP removed
3'b011 - Receiver detected
3'b100 - Either 8B/10B or 128b/130b decode
error and (optionally) RX disparity error
3'b101 - Elastic buffer overflow
3'b110 - Elastic buffer underflow
3'b111 - Receive disparity error, not used if
disparity error is reported using 3'b100.
Signal to clock generation buffer indicating
the rate switch request. Use this signal for
bonding mode only (x2 and x4).
For non-bonded applications (x1), this signal
is internally connected to the local CGB.
Active High. Refer to Table 127
Bit Mappings When the Simplified Interface is
Disabled for more details.
is
on page 143
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