Transmitter Datapath - Intel Cyclone 10 GX User Manual

Figure 180. Enhanced PCS Datapath Diagram
Related Information
Implementing Protocols in Intel Cyclone 10 GX Transceivers

5.2.1. Transmitter Datapath

5.2.1.1. Enhanced PCS TX FIFO
The Enhanced PCS TX FIFO provides an interface between the transmitter channel PCS
and the FPGA fabric. The TX FIFO can operate for phase compensation between the
channel PCS and FPGA fabric. You can also use the TX FIFO as an elastic buffer to
control the input data flow, using
channel bonding. The TX FIFO has a width of 73 bits and a depth of 16 words.
You can set the TX FIFO partially full and empty thresholds through the Transceiver
and PLL Address Map. Refer to the Reconfiguration Interface and Dynamic
Reconfiguration chapter for more details.
The TX FIFO supports the following operating modes:
• Phase Compensation mode
• Register mode
• Interlaken mode
• Basic mode
Related Information
Reconfiguration Interface and Dynamic Reconfiguration
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
284
Transmitter PMA Transmitter Enhanced PCS
PRBS
Generator
Parallel Clock
Receiver PMA Receiver Enhanced PCS
PRBS
Verifier
Clock Generation Block (CGB)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
5. Cyclone 10 GX Transceiver PHY Architecture
PRP
Generator
PRP
Verifier
Parallel Clock
10GBASE-R
BER Checker
Clock Divider
Parallel and Serial Clocks
. The TX FIFO also allows
tx_enh_data_valid
on page 315
UG-20070 | 2018.09.24
FPGA
Fabric
TX
Data &
Control
tx_clkout
tx_pma_div_clkout
rx_pma_div_clkout
RX
Data &
Control
rx_clkout
ATX PLL
fPLL
CMU PLL
Serial Clock
Input Reference Clock
on page 16
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