Standard Pcs Parameters - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
• Using the "Basic (Enhanced PCS)" Configuration

2.4.5. Standard PCS Parameters

This section provides descriptions of the parameters that you can specify to customize
the Standard PCS.
For specific information about configuring the Standard PCS for these protocols, refer
to the sections of this user guide that describe support for these protocols.
Table 24. Standard PCS Parameters
Note:
Parameter
Standard PCS/PMA
interface width
FPGA fabric/Standard
TX PCS interface width
FPGA fabric/Standard
RX PCS interface width
Enable Standard PCS
low latency mode
Table 25. Standard PCS FIFO Parameters
Parameter
TX FIFO mode
RX FIFO mode
Enable
tx_std_pcfifo_full port
Send Feedback
For detailed descriptions of the optional ports that you can enable or disable, refer to the
Standard PCS Ports section.
Range
8, 10, 16, 20 Specifies the data interface width between the Standard PCS and
the transceiver PMA.
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to TX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard TX PCS datapath.
8, 10, 16, 20, 32, 40 Shows the FPGA fabric to RX PCS interface width. This value is
determined by the current configuration of individual blocks within
the Standard RX PCS datapath.
On / Off Enables the low latency path for the Standard PCS. Some of the
functional blocks within the Standard PCS are bypassed to provide
the lowest latency. You cannot turn on this parameter while using
the Basic/Custom w/Rate Match (Standard PCS) specified for
Transceiver configuration rules.
Range
low_latency Specifies the Standard PCS TX FIFO mode. The following modes
are available:
register_fifo
•
fast_register
•
•
low_latency The following modes are available:
register_fifo •
•
On / Off
Enables the
when the standard TX phase compensation FIFO is full. This signal
is synchronous with
on page 158
Description
Description
low_latency: This mode adds 2-3 cycles of latency to the TX
datapath.
register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI.
fast_register: This mode allows a higher maximum frequency
(f ) between the FPGA fabric and the TX PCS at the expense
MAX
of higher latency.
low_latency: This mode adds 2-3 cycles of latency to the RX
datapath.
register_fifo: In this mode the FIFO is replaced by registers
to reduce the latency through the PCS. Use this mode for
protocols that require deterministic latency, such as CPRI or
1588.
tx_std_pcfifo_full
tx_coreclkin
® ®
Intel Cyclone
port. This signal indicates
.
continued...
10 GX Transceiver PHY User Guide
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