Intel Cyclone 10 GX User Manual page 302

5.3.1.2.4. Byte Serializer Serialize x4 Mode
The serialize x4 mode is used in high-speed applications such as the PCIe Gen2
protocol mode, where the FPGA fabric cannot operate as fast as the TX PCS.
In serialize x4 mode, the byte serializer serializes 32-bit data into 8-bit data. As the
parallel data width from the TX FIFO is divided four times, the clock rate is
quadrupled.
After byte serialization, the byte serializer forwards the least significant word first
followed by the most significant word. For example, if the FPGA fabric-to-PCS
Interface width is 32, the byte serializer forwards
followed by
tx_parallel_data[31:24]
Related Information
PCI Express (PIPE)
For more information about using the Serialize x4 mode in the PCIe protocol.
5.3.1.3. 8B/10B Encoder
The 8B/10B encoder takes in 8-bit data and 1-bit control as input and converts them
into a 10-bit output. The 8B/10B encoder automatically performs running disparity
check for the 10-bit output. Additionally, the 8B/10B encoder can control the running
disparity manually using the
Figure 198. 8B/10B Encoder Block Diagrams
When the PCS-PMA Interface Width is 10 bits
To the Serializer
dataout[9:0]
When the PCS-PMA interface width is 10 bits, one 8B/10B encoder is used to convert
the 8-bit data into a 10-bit output. When the PCS-PMA interface width is 20 bits, two
cascaded 8B/10B encoders are used to convert the 16-bit data into a 20-bit output.
The first eight bits (LSByte) is encoded by the first 8B/10B encoder and the next eight
bits (MSByte) is encoded by the second 8B/10B encoder. The running disparity of the
LSByte is calculated first and passed on to the second encoder to calculate the running
disparity of the MSByte.
Note: You cannot enable the 8B/10B encoder when the PCS-PMA interface width is 8 bits or
16 bits.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
302
tx_parallel_data[15:8]
.
on page 122
tx_forcedisp
From the Byte Serializer
datain[7:0]
tx_datak
8B/10B Encoder
tx_forcedisp
tx_dispval
5. Cyclone 10 GX Transceiver PHY Architecture
tx_parallel_data[7:0]
,
tx_parallel_data[23:16]
and ports.
tx_dispval
When the PCS-PMA Interface Width is 20 bits
To the Serializer 8B/10B Encoder
MSB
dataout[19:10]
Encoding
LSB
dataout[9:0]
Encoding
UG-20070 | 2018.09.24
first,
and
From the Byte Serializer
datain[15:8]
tx_datak[1]
tx_forcedisp[1]
tx_dispval[1]
datain[7:0]
tx_datak[0]
tx_forcedisp[0]
tx_dispval[0]
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