Intel Cyclone 10 GX User Manual page 42

Parameter
Enable
tx_std_pcfifo_empty
port
Enable
rx_std_pcfifo_full port
Enable
rx_std_pcfifo_empty
port
Table 26. Byte Serializer and Deserializer Parameters
Parameter
Enable TX byte
serializer
Enable RX byte
deserializer
Table 27. 8B/10B Encoder and Decoder Parameters
Parameter
Enable TX 8B/10B
encoder
Enable TX 8B/10B
disparity control
Enable RX 8B/10B
decoder
Table 28. Rate Match FIFO Parameters
Parameter
RX rate match FIFO mode
RX rate match insert/
delete -ve pattern (hex)
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
42
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Range
On / Off
Enables the
when the standard TX phase compensation FIFO is empty. This
signal is synchronous with
On / Off
Enables the
when the standard RX phase compensation FIFO is full. This signal
is synchronous with
On / Off
Enables the
when the standard RX phase compensation FIFO is empty. This
signal is synchronous with
Range
Disabled Specifies the TX byte serializer mode for the Standard PCS. The
transceiver architecture allows the Standard PCS to operate at
Serialize x2
double or quadruple the data width of the PMA serializer. The byte
Serialize x4
serializer allows the PCS to run at a lower internal clock frequency
to accommodate a wider range of FPGA interface widths.
Serialize x4 is only applicable for PCIe protocol implementation.
Disabled Specifies the mode for the RX byte deserializer in the Standard
PCS. The transceiver architecture allows the Standard PCS to
Deserialize x2
operate at double or quadruple the data width of the PMA
Deserialize x4
deserializer. The byte deserializer allows the PCS to run at a lower
internal clock frequency to accommodate a wider range of FPGA
interface widths. Deserialize x4 is only applicable for PCIe
protocol implementation.
Range
On / Off When you turn on this option, the Standard PCS enables the TX
8B/10B encoder.
On / Off When you turn on this option, the Standard PCS includes disparity
control for the 8B/10B encoder. You can force the disparity of the
8B/10B encoder using the
On / Off When you turn on this option, the Standard PCS includes the
8B/10B decoder.
Range
Disabled Specifies the operation of the RX rate match FIFO in the Standard
PCS.
Basic 10-bit PMA
width Rate Match FIFO in Basic (Single Width) Mode
Basic 20-bit PMA
Rate Match FIFO Basic (Double Width) Mode
width
Rate Match FIFO for GbE
GbE
Transceiver Channel Datapath for PIPE
PIPE
PIPE 0 ppm
User-specified 20 bit Specifies the -ve (negative) disparity value for the RX rate match
pattern FIFO as a hexadecimal string.
Description
port. This signal indicates
tx_std_pcfifo_empty
tx_coreclkin
port. This signal indicates
rx_std_pcfifo_full
.
rx_coreclkin
port. This signal indicates
rx_std_pcfifo_empty
rx_coreclkin
Description
Description
tx_forcedisp
Description
on page 92
on page 123
UG-20070 | 2018.09.24
.
.
control signal.
on page 173
on page 175
continued...
Send Feedback