Intel Cyclone 10 GX User Manual page 233

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
Steps to implement a Multi-Channel x1 Non-Bonded Configuration
1. Choose the PLL IP core (ATX PLL, fPLL, or CMU PLL) you want to instantiate in
your design and instantiate the PLL IP core.
2. Configure the PLL IP core using the IP Parameter Editor
• For the ATX PLL IP core do not include the Master CGB. If your design uses the
ATX PLL IP core and more than 6 channels, the x1 Non-Bonded Configuration
is not a suitable option. Multi-channel xN Non-Bonded or Multi-Channel x1/xN
Non-Bonded are the required configurations when using the ATX PLL IP core
and more than 6 channels in the Native PHY IP core.
• Refer to
Configuration section or the
Bonded Example.
• For the fPLL IP core, set the PLL feedback operation mode to direct.
• For the CMU PLL IP core, specify the reference clock and the data rate. No
special configuration rule is required.
3. Configure the Native PHY IP core using the IP Parameter Editor
• Set the Native PHY IP core TX Channel bonding mode to Non-Bonded.
• Set the number of channels as per your design requirement. In this example,
the number of channels is set to 10.
4. Create a top level wrapper to connect the PLL IP core to the Native PHY IP core.
•
The
speed serial clock.
•
The Native PHY IP core has 10 (for this example)
ports. Each port corresponds to the input of the local CGB of the transceiver
channel.
•
As shown in the figure above, connect the first 6
the first transceiver PLL instance.
•
Connect the remaining 4
PLL instance.
3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration
Using the xN non-bonded configuration reduces the number of PLL resources and the
reference clock sources used.
Send Feedback
Figure 140 on page 234 Implementing Multi-Channel xN Non-Bonded
tx_serial_clk
output
tx_serial_clk input
Figure 141 on page 235 Multi-Channel x1/xN Non-
port of the PLL IP core represents the high
tx_serial_clk input
tx_serial_clk input
to the second transceiver
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