Intel Cyclone 10 GX User Manual page 237

3. PLLs and Clock Networks
UG-20070 | 2018.09.24
•
In this case, the PLL IP core has
[5:0].
•
The Native PHY IP core has
multiplied by the number of transceiver channels (10 in this case). For 10
channels, the bus width will be [59:0].
Note: While connecting
• Connect the PLL IP core to the PHY IP core by duplicating the output of the
PLL[5:0] for the number of channels. For 10 channels, the Verilog syntax for
the input port connection is
({10{tx_bonding_clocks_output}})
Note: Although the above diagram looks similar to the 10-channel non-bonded configuration
example, the clock input ports on the transceiver channels bypass the local CGB in
x6/xN bonding configuration. This internal connection is taken care of when the
Native PHY channel bonding mode is set to Bonded.
Figure 143. x6/xN Bonding Mode —Internal Channel Connections
(1)
(1)
(1)
Note: (1) The local CGB is bypassed by the clock input ports in bonded mode.
Related Information
xN Clock Lines
Information on xN Clock Network Span.
3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
In this bonding mode, the channel span limitations of xN bonding mode are removed.
This is achieved by dividing all channels into multiple bonding groups.
Send Feedback
tx_bonding_clocks
tx_bonding_clocks
avoid any Quartus Prime software fitter errors.
.tx_bonding_clocks
Ch 2
CGB
CDR
Ch 1
CGB
CDR
Ch 0
CGB
CDR
on page 214
tx_bonding_clocks
input bus with width [5:0]
, leave
pll_ref_clk open
.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
output bus with width
to
237