Rate Switch Flag Register - Intel Cyclone 10 GX User Manual

7. Calibration
UG-20070 | 2018.09.24
Bit
0x281[1]
0x281[0]
The PMA 0x281[5:4] is used to isolate the TX and RX calibration busy status. If you
want
rx_cal_busy
0x0 before returning the bus to PreSICE. The channel RX will not be reset due to the
TX calibration. If you want
must set 0x281[4] to 0x0 before returning the bus to PreSICE. The channel TX will not
be reset due to the RX calibration. If you accidentally write 0x00 to 0x281[5:4],
tx_cal_busy
Neither of the 0x281[1:0] registers will go high either.
Table 210. ATX PLL Capability Registers for Calibration Status
Bit
0x280[2]
0x280[1]
Table 211. fPLL Capability Registers for Calibration Status
Bit
0x280[2]
0x280[1]

7.2.6. Rate Switch Flag Register

The rate switch flag is for CDR charge pump calibration. Each SOF has CDR default
charge pump settings. After power up, these settings are loaded into the PreSICE
memory space. If you change the line rate, it may require new charge pump settings,
which will be stored into the Avalon-MM reconfiguration register space. During RX PMA
calibration (including CDR), PreSICE needs to know which set of CDR charge pump
setting to use.
Send Feedback
0x0: The user has control of the internal configuration bus.
PMA channel
rx_cal_busy
0x1: PMA RX calibration is running
0x0: PMA RX calibration is done
PMA channel
tx_cal_busy
0x1: PMA TX calibration is running
0x0: PMA TX calibration is done
unchanged during the TX calibration, you must set 0x281[5] to
tx_cal_busy
and will never be activated to high in the user interface.
rx_cal_busy
PreSICE Avalon-MM interface control. This register is available to check who
controls the bus, no matter if, separate
of AVMM arbitration with PreSICE is enabled or not.
0x1: PreSICE is controlling the internal configuration bus.
0x0: The user has control of the internal configuration bus.
ATX PLL
pll_cal_busy
0x1: ATX PLL calibration is running
0x0: ATX PLL calibration is done
PreSICE Avalon-MM interface control
0x1: PreSICE is controlling the internal configuration bus. This register is available
to check who controls the bus, no matter if, separate
from the status of AVMM arbitration with PreSICE is enabled or not.
0x0: The user has control of the internal configuration bus.
fPLL
pll_cal_busy
0x1: fPLL calibration is running
0x0: fPLL calibration is done
Description
active high
active high
unchanged during the RX calibration, you
Description
reconfig_waitrequest
Description
reconfig_waitrequest
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Intel Cyclone 10 GX Transceiver PHY User Guide
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