Transceiver Blocks Affected By Reset And Powerdown Signals - Intel Cyclone 10 GX User Manual

a. Wait for
rx_analogreset
successfully completed the reset request for assertion.
b. Deassert
2. Wait for
rx_analogreset
completed the reset request for deassertion.
3. Ensure
Wait for
rx_is_lockedtodata
4. Deassert
rx_is_lockedtodata
Figure 160. Dynamic Reconfiguration of Receiver Channel During Device Operation

4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals

You must reset the digital PCS each time you reset the analog PMA or PLL. However,
you can reset the digital PCS block alone.
Table 158. Transceiver Blocks Affected by Specified Reset and Powerdown Signals
Transceiver pll_powerdown
Block
CMU PLL
ATX PLL
fPLL
CDR
Receiver
Standard PCS
Receiver
Enhanced PCS
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
258
rx_analogreset_ack
.
rx_analogreset_ack
rx_analogreset
rx_analogreset_ack
.
rx_analogreset_ack
rx_is_lockedtodata
rx_analogreset_ack
signal.
after a minimum of t
rx_digitalreset
goes high.
Device Power Up
rx_cal_busy
rx_analogreset
rx_analogreset_ack
rx_is_lockedtodata
rx_digitalreset
tx_analogreset
Yes
Yes
Yes
4. Resetting Transceiver Channels
to go high, to ensure successful assertion of
goes high when TRS has
.
to go low, to ensure successful deassertion of
goes low when TRS has successfully
signal goes high after the CDR is locked to data.
to go low before monitoring
(minimum of 4 μs) after
LTD
Legal
Reconfiguration
Window
1 2 3 4
tx_digitalreset rx_analogreset
UG-20070 | 2018.09.24
t min 4 μs
LTD
rx_digitalreset
Yes
Yes
Yes
continued...
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