Intel Cyclone 10 GX User Manual page 356

Address
0x2E1[0]
0x2E2[0]
0x2E2[1]
0x2E2[2]
0x2E2[3]
0x2E2[4]
0x2E2[5]
0x2E2[6]
0x2E2[7]
Table 198. Status Registers for the Native PHY IP Core
Address
0x280[0]
0x280[1]
0x281[0]
0x281[1]
0x281[2]
The following control and status registers are available for the PLL IP cores.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
356
Type Register
RW
rx_seriallpbken
RW
rx_analogreset
RW
rx_digitalreset
RW
tx_analogreset
RW
tx_digitalreset
RW
override_rx_analogr
eset
RW
override_rx_digital
reset
RW
override_tx_analogr
eset
RW
override_tx_digital
reset
Type Register
RO
rx_is_lockedtodata
RO
rx_is_lockedtoref
RO
tx_cal_busy
RO
rx_cal_busy
RO
avmm_busy
6. Reconfiguration Interface and Dynamic Reconfiguration
Enables the
rx_seriallopbken
transceiver. 1'b1 enables reverse serial loopback.
Drives
rx_analogreset
Drives
rx_digitalreset
Drives
tx_analogreset
Drives
tx_digitalreset
Selects whether the receiver listens to the ADME
rx_analogreset
port. 1'b1 indicates the receiver listens to the ADME
rx_analogreset
Selects whether the receiver listens to the ADME
rx_digitalreset
rx_digitalreset
listens to the ADME
Selects whether the receiver listens to the ADME
tx_analogreset
port. 1'b1 indicates the receiver listens to the ADME
tx_analogreset
Selects whether the receiver listens to the ADME
tx_digitalreset
tx_digitalreset
listens to the ADME
Shows the status of the current channel's
rx_is_lockedtodata
receiver is locked to the incoming data.
Shows the status of the current channel's
rx_is_lockedtoref
receiver is locked to the reference clock.
Shows the status of the transmitter calibration
status. 1'b1 indicates the transmitter calibration is in
progress.
Shows the status of the receiver calibration status.
1'b1 indicates the receiver calibration is in progress.
Shows the status of the internal configuration bus
arbitration. 1'b1 indicates PreSICE has control of the
internal configuration bus. 1'b0 indicates the user
has control of the internal configuration bus. Refer to
the Arbitration section for more details. For more
details about calibration registers and performing
user recalibration, refer to the Calibration chapter.
UG-20070 | 2018.09.24
Description
feature in the
when the override is set.
when the override is set.
when the override is set.
when the override is set.
register or the
rx_analogreset
register.
register or the
port. 1'b1 indicates the receiver
register.
rx_digitalreset
register or the
tx_analogreset
register.
register or the
port. 1'b1 indicates the receiver
register.
tx_digitalreset
Description
signal. 1'b1 indicates the
signal. 1'b1 indicates the
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