Cyclone 10 Gx Transceiver Register Map; Reconfiguration Interface And Dynamic Reconfiguration Revision History - Intel Cyclone 10 GX User Manual

• Reconfiguration from a bonded configuration to a non-bonded configuration, or
vice versa
• Reconfiguration from a bonded protocol to another bonded protocol
• Reconfiguration from PCIe (with Hard IP) to PCIe (without Hard IP) or non-PCIe
bonded protocol switching
• Switching between bonding schemes, such as xN to feedback compensation
• Master CGB reconfiguration
• Switching between two master CGBs
• Serialization factor changes on bonded channels
• TX PLL switching on bonded channels
Note: Transceiver Native PHY IP non-bonded configuration to another Transceiver Native PHY
IP non-bonded configuration is supported.

6.19. Cyclone 10 GX Transceiver Register Map

The transceiver register map provides a list of available PCS, PMA, and PLL addresses
that are used in the reconfiguration process.
Use the register map in conjunction with a transceiver configuration file generated by
the Cyclone 10 GX Native PHY IP core. This configuration file includes details about the
registers that are set for a specific transceiver configuration. Do not use the register
map to locate and modify specific registers in the transceiver. Doing so may result in
an illegal configuration. Refer to a valid transceiver configuration file for legal register
values and combinations.
The register map is provided as an Excel spreadsheet for easy search and filtering.
Related Information
Cyclone 10 GX Transceiver Register Map
6.20. Reconfiguration Interface and Dynamic Reconfiguration
Revision History
Document
Version
2017.11.06 Made the following changes:
• Added a note to the "Using PRBS Data Pattern Generator and Checker" chapter.
• Updated "Variable Gain Amplifier (VGA) Voltage Swing Select" from "radp_vga_sel_0 to
radp_vga_sel_7" to "radp_vga_sel_0 to radp_vga_sel_4".
• Added sentence "The dynamic reconfiguration interface is compliant to the AVMM specifications".
• Changed VGA select in Register Map for CTLE Setting from 3'b00-3'b111 to 3'b00-3'b100.
2017.05.08 Initial release.
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Intel Cyclone 10 GX Transceiver PHY User Guide
372
6. Reconfiguration Interface and Dynamic Reconfiguration
Changes
UG-20070 | 2018.09.24
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