Cyclone 10 Gx Transceiver Protocols And Phy Ip Support - Intel Cyclone 10 GX User Manual

2.3. Cyclone 10 GX Transceiver Protocols and PHY IP Support

Table 3. Cyclone 10 GX Transceiver Protocols and PHY IP Support
Protocol
PCIe Gen2 x1, x2, x4
PCIe Gen1 x1, x2, x4
1000BASE-X Gigabit
Ethernet
1000BASE-X Gigabit
Ethernet with 1588
10GBASE-R
10GBASE-R 1588
40GBASE-R
Interlaken (CEI-6G-SR
(6)
and CEI-11G-SR)
OTU-1 (2.7G)
(1)
Hard IP for PCI Express is also available as a separate IP core.
(2)
For x2 and x4 modes, select PCIe PIPE Gen2 x8. Then change the number of data channels
from 8 to 4.
(3)
For PCIe Gen1 x1 mode, select PCIe PIPE Gen2 x1 mode. Then change the transceiver
configuration rule from Gen 2 PIPE to Gen 1 PIPE.
For PCIe Gen1 x2 and x4 mode, select PCIe PIPE Gen2 x8. Then change the transceiver
configuration rule from Gen2 PIPE to Gen1 PIPE and number of data channels from 8 to 2 or 4.
(4)
Select the 10GBASE-R preset. Then change the transceiver configuration rule from 10GBASE-R
to 10GBASE-R 1588.
(5)
To implement 40GBASE-R using the Low Latency Enhanced PCS preset, change the number of
data channels to four and select appropriate PCS- FPGA Fabric and PCS-PMA width.
(6)
Link training, auto speed negotiation and sequencer functions are not included in the Native
PHY IP. The user would have to create soft logic to implement these functions when using
Native PHY IP.
A Transmit PCS soft bonding logic required for multi-lane bonding configuration is provided in
the design example.
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
24
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
Transceiver PHY IP PCS Support
Core
Native PHY IP (PIPE)
core/Hard IP for PCI
(1)
Express
Native PHY IP (PIPE)
core/Hard IP for PCI
(1)
Express
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Native PHY IP core
Transceiver
Configuration Rule
Standard Gen2 PIPE
Standard Gen1 PIPE
Standard GbE
Standard GbE 1588
Enhanced 10GBASE-R
Enhanced 10GBASE-R 1588
Enhanced Basic (Enhanced PCS)
Enhanced Interlaken
Standard Basic/Custom
(Standard PCS)
UG-20070 | 2018.09.24
Protocol Preset
(2)
PCIe PIPE Gen2 x1
(3)
User created
GIGE - 1.25 Gbps
GIGE - 1.25 Gbps
1588
10GBASE-R Low
Latency
(4)
10GBASE-R
Low Latency Enhanced
(5)
PCS
Interlaken
10x12.5Gbps
Interlaken
6x10.3Gbps
Interlaken
1x6.25Gbps
User created
continued...
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