Transceiver Channel Datapath For Pipe; Supported Pipe Features - Intel Cyclone 10 GX User Manual

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Related Information
PHY Interface For the PCI Express, SATA, and USB 3.1 Architectures

2.7.1. Transceiver Channel Datapath for PIPE

Figure 57. Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
Transmitter PMA
Receiver PMA

2.7.2. Supported PIPE Features

PIPE Gen1 and Gen2 configurations support different features.
Table 118. Supported Features for PIPE Configurations
x1, x2, x4 link configurations
PCIe-compliant synchronization state machine
Total 600 ppm clock rate compensation between transmitter reference clock
and receiver reference clock
Transmitter driver electrical idle
Receiver detection
8B/10B encoding/decoding disparity control
Power state management
Receiver PIPE status encoding
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate
Dynamic transmitter margining for differential output voltage control
Dynamic transmitter buffer de-emphasis of –3.5 dB and –6 dB
PCS PMA interface width (bits)
Receiver Electrical Idle Inference (EII)
Send Feedback
PRBS
Generator
PRBS
Verifier
Protocol Feature
pipe_rxstatus[2:0]
Transmitter Standard PCS
Receiver Standard PCS
Gen1
(2.5 Gbps)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
10
Your implementation in
the FPGA fabric
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
FPGA
Fabric
Gen2
(5 Gbps)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
10
Your
implementation
in the FPGA
fabric
123