Intel Cyclone 10 GX User Manual page 150

Table 131. Channel Width Options for Supported Serial Data Rates
Serial Data
Rate
(Mbps)
8-Bit
(25)
614.4
1228.8
2457.6
3072
4915.2
6144
2.8.1.1. TX PLL Selection for CPRI
Choose a transmitter PLL that fits your required data rate.
Table 132. TX PLL Supported Data Rates
ATX and fPLL support the clock bonding feature.
TX PLLs
ATX
fPLL
CMU
Note: • Channels that use the CMU PLL cannot be bonded. The CMU PLL that provides the
clock can only drive channels in the transceiver bank where it resides.
• Over-sampling is required to implement 614.4 Mbps.
2.8.1.2. Auto-Negotiation
When auto-negotiation is required, the channels initialize at the highest supported
frequency and switch to successively lower data rates if frame synchronization is not
achieved. If your design requires auto-negotiation, choose a base data rate that
minimizes the number of PLLs required to generate the clocks required for data
transmission.
By selecting an appropriate base data rate, you can change data rates by changing the
local clock generation block (CGB) divider. If a single base data rate is not possible,
you can use an additional PLL to generate the required data rates.
Table 133. Recommended Base Data Rates and Clock Generation Blocks for Available
Data Rates
Data Rate (Mbps)
1228.8
2457.6
(25)
Over-sampling is required to implement 614.4Mbps
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
150
Channel Width (FPGA-PCS Fabric)
8/10 Bit Width
16-Bit
Yes Yes
Yes Yes
Yes Yes
Yes Yes
N/A N/A
N/A N/A
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144
614.4, 1228.8, 2457.6, 3072, 4915.2, 6144
Base Data Rate (Mbps)
4915.2
4915.2
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
16-Bit
N/A
Yes
Yes
Yes
Yes
Yes
Supported Data Rate (Mbps)
UG-20070 | 2018.09.24
16/20 Bit Width
32-Bit
N/A
Yes
Yes
Yes
Yes
Yes
Local CGB Divider
4
2
continued...
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