Phy Layer Transceiver Components - Intel Cyclone 10 GX User Manual

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1. Intel Cyclone 10 GX Transceiver PHY Overview
UG-20070 | 2018.09.24
Figure 5. Transceiver Bank Architecture
Legend:
Note: This figure is a high level overview of the transceiver bank architecture. For details
about the available clock networks refer to the PLLs and Clock Networks chapter.
Related Information
PLLs and Clock Networks

1.2.2. PHY Layer Transceiver Components

Transceivers in Intel Cyclone 10 GX devices support both Physical Medium Attachment
(PMA) and Physical Coding Sublayer (PCS) functions at the physical (PHY) layer.
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Six-Channel Transceiver Bank
CH5
PMA
Channel PLL
Local CGB5
(CDR Only)
CH4
PMA
Channel PLL
Local CGB4
(CMU/CDR)
CH3
PMA
Channel PLL
Local CGB3
(CDR Only)
CH2
PMA
Channel PLL
Local CGB2
(CDR Only)
CH1
PMA
Channel PLL
Local CGB1
(CMU/CDR)
CH0
PMA
Channel PLL
Local CGB0
(CDR Only)
4-Channel transceiver bank
on page 198
Clock
Distribution
Network
PCS
PCS
PCS
PCS
PCS
PCS
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Intel Cyclone
fPLL1
Master
CGB1
FPGA Core
ATX
Fabric
PLL1
fPLL0
Master
CGB0
ATX
PLL0
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10 GX Transceiver PHY User Guide
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