Intel Cyclone 10 GX User Manual page 125

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and
Status State Machine (LTSSM) enters the Polling.Compliance substate. The
Polling.Compliance substate assesses if the transmitter is electrically compliant with
the PCIe voltage and timing specifications.
2.7.2.1.5. Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status
signal
pipe_rx_status[2:0]
PHY-MAC layer for its operation. The PIPE interface block receives status signals from
the transceiver channel PCS and PMA blocks, and encodes the status on the
pipe_rx_status[2:0]
on the
pipe_rx_status[2:0]
2.7.2.1.6. Receiver Detection
The PIPE interface block in Cyclone 10 GX transceivers provides an input signal
pipe_tx_detectrx_loopback[0:0]
protocol requires this signal to be high during the Detect state of the LTSSM. When the
pipe_tx_detectrx_loopback[0:0]
PIPE interface block sends a command signal to the transmitter driver in that channel
to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer
must always be in the electrical idle state. After receiving this command signal, the
receiver detect circuitry creates a step voltage at the output of the transmitter buffer.
The time constant of the step voltage on the trace increases if an active receiver that
complies with the PCIe input impedance requirements is present at the far end. The
receiver detect circuitry monitors this time constant to determine if a receiver is
present.
Note: For the receiver detect circuitry to function reliably, the transceiver on-chip
termination must be used. Also, the AC-coupling capacitor on the serial link and the
receiver termination values used in your system must be compliant with the PCIe Base
Specification 2.0.
The PIPE core provides a 1-bit PHY status signal
receiver status signal
detected, as per the PIPE 2.0 specifications.
2.7.2.1.7. Gen1 and Gen2 Clock Compensation
In compliance with the PIPE specification, Intel Cyclone 10 GX receiver channels have
a rate match FIFO to compensate for small clock frequency differences up to ±600
ppm between the upstream transmitter and the local receiver clocks.
Consider the following guidelines for PIPE clock compensation:
• Insert or delete one SKP symbol in an SKP ordered set.
• Minimum limit is imposed on the number of SKP symbols in SKP ordered set after
deletion. An ordered set may have an empty COM case after deletion.
• Maximum limit is imposed on the number of the SKP symbols in the SKP ordered
set after insertion. An ordered set may have more than five symbols after
insertion.
Send Feedback
for each channel. This status signal is used by the
signal to the FPGA fabric. The encoding of the status signals
signal conforms to the PCIe specification.
for the receiver detect operation. The PCIe
signal is asserted in the P1 power state, the
pipe_rx_status[2:0]
pipe_phy_status[0:0]
to indicate whether a receiver is
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Intel Cyclone 10 GX Transceiver PHY User Guide
and a 3-bit
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