Intel Cyclone 10 GX User Manual page 294

Table 168. Supported PRBS Patterns
PRBS Pattern
7 6
PRBS7: x + x + 1
9 5
PRBS9: x + x + 1
15 14
PRBS15: x + x + 1
23 18
PRBS23: x + x + 1
31 28
PRBS31: x + x + 1
Figure 189. PRBS9 Verify Serial Implementation
The PRBS checker has the following control and status signals available to the FPGA
fabric:
•
rx_prbs_done
stays high until you reset it with
•
rx_prbs_err
allow you to capture it in the RX FPGA CLK domain.
•
rx_prbs_err_clr
Enable the PRBS checker control and status ports through the Native PHY IP
Parameter Editor in the Quartus Prime software.
5.2.2.7. Pseudo Random Pattern Verifier
The Pseudo Random Pattern (PRP) verifier is available for 10GBASE-R and 10GBASE-R
1588 protocol modes. The PRP verifier block operates in conjunction with the
descrambler. The PRP verifier monitors the output of the descrambler when block
synchronization is achieved.
The
rx_prbs_err
verifier.
The PRP verifier:
• Searches for a test pattern (two local faults, or all 0s) or its inverse
• Tracks the number of mismatches with a 16-bit error counter
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
294
10 bit PCS-PMA width
Yes
PRBS datain
S0 S1
PRBS Error
—Indicates the PRBS sequence has completed one full cycle. It
—Goes high if an error occurs. This signal is pulse-extended to
—Used to reset the
error signal is shared between the PRBS checker and the PRP
5. Cyclone 10 GX Transceiver PHY Architecture
Yes
Yes
Yes
Yes
Yes
S4 S5
.
rx_prbs_err_clr
signal.
rx_prbs_err
UG-20070 | 2018.09.24
64 bit PCS-PMA width
S8
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