Intel Cyclone 10 GX User Manual page 104

6. Create a transceiver reset controller. You can use your own reset controller or use
the Intel Cyclone 10 GX Transceiver Native PHY Reset Controller IP.
7. Connect the Intel Cyclone 10 GX Transceiver Native PHY to the PLL IP and the
reset controller.
Figure 48. Connection Guidelines for a 10GBASE-R with IEEE 1588v2 PHY Design
through XGMII
8. Simulate your design to verify its functionality.
2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R and 10GBASE-R with
IEEE 1588v2
This section contains the recommended parameter values for this protocol. Refer to
Using the Cyclone 10 GX Transceiver Native PHY IP Core for the full range of
parameter values.
Table 89. General and Datapath Parameters
The first two sections of the Transceiver Native PHY parameter editor provide a list of general and datapath
options to customize the transceiver.
Message level for rule violations
Transceiver Configuration Rule
Transceiver mode
Number of data channels
Data rate
Enable datapath and interface reconfiguration
Enable simplified data interface
Table 90. TX PMA Parameters
TX channel bonding mode
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
104
To MAC/RS
Interface
FIFO in the
64d + 8c
FPGA core
for TX
FIFO in the
FPGA core
64d + 8c
for RX
Parameter
Parameter
2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
PLL IP
Cyclone 10 Transceiver
Native PHY
error, warning
10GBASE-R
10GBASE-R 1588
TX / RX Duplex, TX Simplex, RX Simplex
1 to 12
10312.5 Mbps
Off
On
Off
Not bonded
1, 2, 4, 8
1, 2, 3, 4
0, 1, 2, 3
UG-20070 | 2018.09.24
Reset
Controller
Medium
Range
Range
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