Intel Cyclone 10 GX User Manual page 85

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Table 74. Interlaken Frame Synchronizer Parameters
Enable Interlaken frame synchronizer
Frame synchronizer metaframe length
Enable rx_enh_frame port
Enable rx_enh_frame_lock port
Enable rx_enh_frame_diag_status port
Table 75. Interlaken CRC-32 Generator and Checker Parameters
Enable Interlaken TX CRC-32 generator
Enable Interlaken TX CRC-32 generator error
insertion
Enable Interlaken RX CRC-32 checker
Enable rx_enh_crc32_err port
Table 76. Scrambler and Descrambler Parameters
Enable TX scrambler (10GBASE-R / Interlaken)
TX scrambler seed (10GBASE-R / Interlaken)
Enable RX descrambler (10GBASE-R / Interlaken)
Table 77. Interlaken Disparity Generator and Checker Parameters
Enable Interlaken TX disparity generator
Enable Interlaken RX disparity checker
Enable Interlaken TX random disparity bit
Table 78. Block Sync Parameters
Enable RX block synchronizer
Enable rx_enh_blk_lock port
Table 79. Gearbox Parameters
Enable TX data bitslip
Enable TX data polarity inversion
Enable RX data bitslip
Send Feedback
Parameter
Parameter
Parameter
Parameter
Parameter
Parameter
Value
On
5 to 8192 (Intel recommends a minimum metaframe
length of 128)
On
On / Off
On / Off
Value
On
On / Off
On
On / Off
Value
On
0x1 to 0x3FFFFFFFFFFFFFF
On
Value
On
On
On / Off
Value
On
On / Off
Value
Off
On / Off
Off
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
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