Intel Cyclone 10 GX User Manual page 83

2. Implementing Protocols in Intel Cyclone 10 GX Transceivers
UG-20070 | 2018.09.24
Actual PCS TX channel bonding master
TX local clock division factor
Number of TX PLL clock inputs per channel
Initial TX PLL clock input selection
Enable tx_pma_clkout port
Enable tx_pma_div_clkout port
tx_pma_div_clkout division factor
Enable tx_pma_elecidle port
Enable rx_seriallpbken port
Table 71. RX PMA Parameters
Number of CDR reference clocks
Selected CDR reference clock
Selected CDR reference clock frequency
PPM detector threshold
CTLE adaptation mode
Enable rx_pma_clkout port
Enable rx_pma_div_clkout port
rx_pma_div_clkout division factor
Enable rx_pma_clkslip port
Enable rx_is_lockedtodata port
Enable rx_is_lockedtoref port
Enable rx_set_locktodata and rx_set_locktoref ports
Enable rx_seriallpbken port
Enable PRBS verifier control and status ports
Table 72. Enhanced PCS Parameters
Enhanced PCS / PMA interface width
FPGA fabric / Enhanced PCS interface width
Enable 'Enhanced PCS' low latency mode
Send Feedback
Parameter
Parameter
Parameter
Value
If TX channel bonding mode is set to PMA and PCS
bonding, then:
0, 1, 2, 3,...,[Number of data channels – 1]
If TX channel bonding mode is not bonded, then:
1, 2, 4, 8
If TX channel bonding mode is not bonded, then:
1, 2, 3, 4
0
On / Off
On / Off
When Enable tx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
On / Off
On / Off
Value
1 to 5
0 to 4
Select legal range defined by the Quartus Prime software
100, 300, 500, 1000
manual,
On / Off
On / Off
When Enable rx_pma_div_clkout port is On, then:
Disabled, 1, 2, 33, 40, 66
On / Off
On / Off
On / Off
On / Off
On / Off
On / Off
Value
32, 40, 64
67
Allowed when the PMA interface width is 32 and preset
variations for data rate is 10.3125 Gbps or 6.25 Gbps;
otherwise Off
® ®
Intel Cyclone 10 GX Transceiver PHY User Guide
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