Altera cyclone V Technical Reference page 3043

cv_5v4
2016.10.28
Register
ic_intr_stat
20-38
ic_intr_mask
20-41
ic_raw_intr_stat
page 20-44
ic_rx_tl on page 20-
46
ic_tx_tl on page 20-
47
ic_clr_intr on page
20-48
ic_clr_rx_under
page 20-49
ic_clr_rx_over
page 20-50
ic_clr_tx_over
page 20-50
ic_clr_rd_req
20-51
ic_clr_tx_abrt
page 20-52
ic_clr_rx_done
page 20-53
ic_clr_activity
page 20-54
ic_clr_stop_det
page 20-54
ic_clr_start_det
page 20-55
ic_clr_gen_call
page 20-56
ic_enable on page 20-
57
ic_status on page 20-
58
ic_txflr on page 20-
60
ic_rxflr on page 20-
61
I2C Controller
Send Feedback
Offset Width Acces
on page 0x2C
on page 0x30
on 0x34
0x38
0x3C
0x40
on 0x44
on 0x48
on 0x4C
on page 0x50
on 0x54
on 0x58
on 0x5C
on 0x60
on 0x64
on 0x68
0x6C
0x70
0x74
0x78
Reset Value
s
32 RO 0x0
32 RW 0x8FF
32 RO 0x0
32 RW 0x0
32 RW 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RO 0x0
32 RW 0x0
32 RO 0x6
32 RO 0x0
32 RO 0x0
I2C Module Address Map
Description
Interrupt Status Register
Interrupt Mask Register
Raw Interrupt Status Register
Receive FIFO Threshold Register
Transmit FIFO Threshold Level
Register
Combined and Individual
Interrupt Register
Rx Under Interrupt Register
RX Over Interrupt Register
TX Over Interrupt Register
Interrupt Read Request Register
Tx Abort Interrupt Register
Rx Done Interrupt Register
Activity Interrupt Register
Stop Detect Interrupt Register
Start Detect Interrupt Register
GEN CALL Interrupt Register
Enable Register
Status Register
Transmit FIFO Level Register
Receive FIFO Level Register
Altera Corporation
20-25