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5.2.1.1.
MEMORY READ TRANSACTIONS
code read
data read
Memory Read Transactions perform reads of memory or memory-mapped I/O. REQa[1]# indi-
cates whether the read is for code or data. This can be used to make cache coherency assump-
tions (see Chapter 7, Cache Protocol).
5.2.1.2.
MEMORY WRITE TRANSACTIONS
may not be retried
may be retried
Memory Write Transactions perform writes to memory or memory-mapped I/O. REQa[1]# in-
dicates whether the write transaction is a writeback and may not be retried. REQa[1]# asserted
indicates that the write transaction may be retried. REQa[1]# is asserted by a non-cacheable
(DMA) agent to write data to memory. The Pentium Pro processor asserts REQa[1]# when writ-
ing through the cache and when evicting a full Write Combining Buffer. This transaction is
snooped and can receive an Implicit Writeback Response. When REQa[1]# is deasserted, no
agent may assert DEFER# to retry the transaction. A writeback caching agent must deassert
REQa[1]# when writing back a modified cache line to memory. If deasserted and this transaction
hits a valid line in a snooping cache, a cache coherency violation has occurred.
5.2.1.3.
MEMORY (READ) INVALIDATE TRANSACTIONS
Memory (Read) Invalidate
An agent issues a Read Invalidate Transaction to satisfy an internal cache line fill and obtain ex-
clusive ownership of the line. All snooping agents will invalidate the line addressed by this trans-
action. A Read Invalidate transaction has BE[7:0]# = FFH and LEN[1:0]# = 10B. Note that if
the issuing agent already has the line in the shared state, it need only invalidate the line in other
caches to allow a transition to the exclusive state. In this case the requesting agent issues a zero
length transaction (BE[7:0]# = 00H and LEN[1:0]# = 00) indicating that no data is required.
BUS TRANSACTIONS AND OPERATIONS
REQa[2:0]#
1
D/C#=0
1
D/C#=1
REQa[2:0]#
1
W/WB#=0
1
W/WB#=1
REQa[2:0]#
0
0
0
1
1
1
0
5-5
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