Intel PXA270 Manuals

Table of Contents

• • 3

    Table of Contents
  • 9

    Revision History
  • 11

    Introduction
    • 11

      About This Document
  • 11

    Related Documentation
    • 12

      High-Level Overview
      • 13

        Intel Xscale® Microarchitecture and Intel Xscale® Core
  • 13

    Pxa27X Processor Block Diagram
    • 14

      Intel Xscale® Microarchitecture Features
    • 14

      Intel® Wireless MMX™ Technology
    • 15

      Memory Architecture
      • 15

        Caches
      • 15

        Internal Memories
      • 15

        External Memory Controller
      • 15

        Processor Internal Communications
        • 15

          System Bus
        • 16

          Peripheral Bus
        • 16

          Peripherals in the Processor
      • 17

        Wireless Intel Speedstep® Technology
    • 18

      Intel Xscale® Microarchitecture Compatibility
      • 18

        Pxa27X Processor Performance Features

• 21

  2 Microarchitecture Overview

  • 21

    Introduction
  • 21

    Intel Xscale® Microarchitecture Pipeline
    • 21

      General Pipeline Characteristics
      • 21

        Pipeline Organization
  • 21

    Intel Xscale® Microarchitecture RISC Superpipeline
    • 22

      Out of Order Completion
    • 22

      Use of Bypassing
    • 22

      Instruction Flow Through the Pipeline
  • 22

    Pipelines and Pipe Stages
    • 23

      ARM* V5TE Instruction Execution
    • 23

      Pipeline Stalls
    • 23

      Main Execution Pipeline
      • 23

        F1 / F2 (Instruction Fetch) Pipestages
      • 24

        Instruction Decode (ID) Pipestage
      • 24

        Register File / Shifter (RF) Pipestage
      • 24

        Execute (X1) Pipestages
      • 25

        Execute 2 (X2) Pipestage
      • 25

        Write-Back (WB)
      • 25

        Memory Pipeline
        • 25

          D1 and D2 Pipestage
      • 25

        Multiply/Multiply Accumulate (MAC) Pipeline
        • 26

          Behavioral Description
        • 26

          Perils of Superpipelining
    • 27

      Intel® Wireless MMX™ Technology Pipeline
      • 27

        Execute Pipeline Thread
        • 27

          ID Stage
        • 27

          RF Stage
  • 27

    Intel® Wireless MMX™ Technology Pipeline Threads and Relation with Intel Xscale® Microarchitecture Pipeline
    • 28

      X1 Stage
    • 28

      X2 Stage
    • 28

      XWB Stage
    • 28

      Multiply Pipeline Thread
      • 28

        M1 Stage
      • 28

        M2 Stage
      • 29

        Memory Pipeline Thread
        • 29

          D1 Stage
        • 29

          D2 Stage
        • 29

          DWB Stage

• 31

  3 System Level Optimization

  • 31

    Optimizing Frequency Selection
  • 31

    Memory System Optimization
    • 31

      Optimal Setting for Memory Latency and Bandwidth
  • 31

    External SDRAM Access Latency and Throughput for Different Frequencies (Silicon Measurement Pending)
    • 32

      Alternate Memory Clock Setting
  • 32

    Internal SRAM Access Latency and Throughput for Different Frequencies (Silicon Measurement Pending)
    • 33

      Page Table Configuration
      • 33

        Page Attributes for Instructions
      • 33

        Page Attributes for Data Access
  • 33

    Data Cache and Buffer Behavior When X = 1
    • 34

      Optimizing for Instruction and Data Caches
      • 34

        Increasing Instruction Cache Performance
  • 34

    Data Cache and Buffer Operation Comparison for Intel® SA-1110 and Intel Xscale
    • 35

      Round Robin Replacement Cache Policy
    • 35

      Code Placement to Reduce Cache Misses
    • 35

      Locking Code Into the Instruction Cache
    • 35

      Increasing Data Cache Performance
      • 36

        Cache Configuration
      • 36

        Creating Scratch RAM in the Internal SRAM
      • 37

        Creating Scratch RAM in Data Cache
      • 37

        Reducing Memory Page Thrashing
      • 38

        Using Mini-Data Cache
      • 38

        Reducing Cache Conflicts, Pollution and Pressure
      • 38

        Optimizing TLB (Translation Lookaside Buffer) Usage
    • 39

      Optimizing for Internal Memory Usage
      • 39

        LCD Frame Buffer
      • 39

        Buffer for Capture Interface
      • 40

        Buffer for Context Switch
      • 40

        Scratch Ram
      • 40

        OS Acceleration
      • 40

        Increasing Preloads for Memory Performance
    • 40

      Optimization of System Components
      • 41

        LCD Controller Optimization
        • 41

          Bandwidth and Latency Requirements for LCD
        • 43

          Frame Buffer Placement for LCD Optimization
        • 44

          LCD Display Frame Buffer Setting
        • 44

          LCD Color Conversion HW
        • 44

          Arbitration Scheme Tuning for LCD
      • 45

        Optimizing Arbiter Settings
        • 45

          Arbiter Functionality
        • 45

          Determining the Optimal Weights for Clients
        • 46

          Taking Advantage of Bus Parking
        • 46

          Dynamic Adaptation of Weights
      • 47

        Usage of DMA
      • 47

        Peripheral Bus Split Transactions
  • 47

    Memory to Memory Performance Using DMA for Different Memories and Frequencies

• 49

  4 Intel Xscale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization

  • 49

    Introduction
  • 49

    General Optimization Techniques
    • 49

      Conditional Instructions and Loop Control
    • 50

      Program Flow and Branch Instructions
    • 53

      Optimizing Complex Expressions
      • 54

        Bit Field Manipulation
    • 54

      Optimizing the Use of Immediate Values
    • 55

      Optimizing Integer Multiply and Divide
    • 56

      Effective Use of Addressing Modes
  • 56

    Instruction Scheduling for Intel Xscale® Microarchitecture and Intel® Wireless MMX™ Technology
    • 56

      Instruction Scheduling for Intel Xscale® Microarchitecture
      • 56

        Scheduling Loads
      • 59

        Increasing Load Throughput
      • 60

        Increasing Store Throughput
      • 61

        Scheduling Load Double and Store Double (LDRD/STRD)
      • 62

        Scheduling Load and Store Multiple (LDM/STM)
      • 63

        Scheduling Data-Processing
      • 63

        Scheduling Multiply Instructions
      • 64

        Scheduling SWP and SWPB Instructions
      • 65

        Scheduling the MRA and MAR Instructions (MRRC/MCRR)
      • 65

        Scheduling MRS and MSR Instructions
      • 66

        Scheduling Coprocessor 15 Instructions
    • 66

      Instruction Scheduling for Intel® Wireless MMX™ Technology
      • 66

        Increasing Load Throughput On Intel® Wireless MMX™ Technology
      • 67

        Scheduling the WMAC Instructions
      • 68

        Scheduling the TMIA Instruction
      • 69

        Scheduling the WMUL and WMADD Instructions
  • 69

    SIMD Optimization Techniques
    • 69

      Software Pipelining
      • 71

        General Remarks On Software Pipelining
    • 71

      Multi-Sample Technique
      • 73

        General Remarks On Multi-Sample Technique
    • 73

      Data Alignment Techniques
  • 74

    Porting Existing Intel® MMX™ Technology Code to Intel® Wireless MMX™ Technology
    • 75

      Intel® Wireless MMX™ Technology Instruction Mapping
  • 75

    Pxa27X Processor Mapping to Intel® Wireless MMX™ Technology and SSE
    • 76

      Unsigned Unpack Example
    • 77

      Signed Unpack Example
    • 77

      Interleaved Pack with Saturation Example
    • 77

      Optimizing Libraries for System Performance
      • 77

        Case Study 1: Memory-To-Memory Copy
      • 78

        Case Study 2: Optimizing Memory Fill
      • 79

        Case Study 3: Dot Product
      • 80

        Case Study 4: Graphics Object Rotation
      • 81

        Case Study 5: 8X8 Block 1/2X Motion Compensation
    • 82

      Intel® Performance Primitives
    • 83

      Instruction Latencies for Intel Xscale® Microarchitecture
      • 83

        Performance Terms
      • 85

        Branch Instruction Timings
      • 86

        Data Processing Instruction Timings
      • 87

        Multiply Instruction Timings
      • 88

        Saturated Arithmetic Instructions
      • 89

        Status Register Access Instructions
      • 89

        Load/Store Instructions
      • 90

        Semaphore Instructions
      • 90

        CP15 and CP14 Coprocessor Instructions
      • 90

        Miscellaneous Instruction Timing
      • 91

        Thumb* Instructions
    • 91

      Instruction Latencies for Intel® Wireless MMX™ Technology
    • 93

      Performance Hazards
      • 93

        Data Hazards
      • 93

        Resource Hazard
        • 94

          Execution Pipeline
        • 95

          Multiply Pipeline
        • 96

          Memory Control Pipeline
        • 97

          Coprocessor Interface Pipeline
        • 97

          Multiple Pipelines

• 99

  5 High Level Language Optimization

  • 99

    C and C++ Level Optimization
    • 99

      Efficient Usage of Preloading
      • 99

        Preload Considerations
      • 101

        Preload Loop Limitations
      • 102

        Coding Technique with Preload
    • 104

      Array Merging
    • 106

      Cache Blocking
    • 106

      Loop Interchange
    • 107

      Loop Fusion
    • 107

      Loop Unrolling
    • 109

      Loop Conditionals
    • 110

      If-Else Versus Switch Statements
    • 110

      Nested If-Else and Switch Statements
    • 110

      Locality in Source Code
    • 110

      Choosing Data Types
    • 110

      Data Alignment for Maximizing Cache Usage
    • 112

      Placing Literal Pools
    • 112

      Global Versus Local Variables
    • 112

      Number of Parameters in Functions
    • 112

      Other General Optimizations

• 115

  6 Power Optimization

  • 115

    Introduction
  • 115

    Optimizations for Core Power
    • 115

      Code Optimization for Power Consumption
    • 115

      Switching Modes for Saving Power
      • 115

        Normal Mode
      • 116

        Idle Mode
      • 116

        Deep Idle Mode
      • 116

        Standby Mode
      • 116

        Sleep Mode
      • 116

        Deep-Sleep Mode
    • 117

      Wireless Intel Speedstep® Technology Power Manager
    • 117

      System Bus Frequency Selection
      • 118

        Fast-Bus Mode
      • 118

        Half-Turbo Mode
  • 119

    Optimizations for Memory and Peripheral Power
    • 119

      Improved Caching and Internal Memory Usage
    • 119

      SDRAM Auto Power Down (APD)
    • 119

      External Memory Bus Buffer Strength Registers
    • 119

      Peripheral Clock Gating
    • 119

      LCD Subsystem
    • 120

      Voltage and Regulators
    • 120

      Operating Mode Recommendations for Power Savings
      • 120

        Normal Mode
      • 120

        Idle Mode
      • 121

        Deep-Idle Mode
      • 121

        Standby Mode
      • 121

        Sleep Mode
      • 121

        Deep-Sleep Mode
  • 123

    Performance Checklist
    • 123

      Performance Optimization Tips
    • 124

      Power Optimization Guidelines