Intel PXA270 Computer module Manuals

Manuals and User Guides for Intel PXA270 Computer module. We have 1 Intel PXA270 Computer module manual available for free PDF download: Optimization Manual

Intel PXA270 Optimization Manual

Intel PXA270 Optimization Manual (144 pages)

PXA27x Processor Family

Brand: Intel | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table of Contents
3
Revision History
9
1 Introduction

11
- About this Document
  11
- Related Documentation
  11
  - High-Level Overview
    12
    
    Intel Xscale® Microarchitecture and Intel Xscale® Core
    13
- Pxa27X Processor Block Diagram
  13
  - Intel Xscale® Microarchitecture Features
    14
  - Intel® Wireless MMX™ Technology
    14
  - Memory Architecture
    15
    
    Caches
    15
    
    External Memory Controller
    15
    
    Internal Memories
    15
    
    Processor Internal Communications
    15
    
    System Bus
    15
    
    Peripheral Bus
    16
    
    Peripherals in the Processor
    16
    
    Wireless Intel Speedstep® Technology
    17
  - Intel Xscale® Microarchitecture Compatibility
    18
    
    Pxa27X Processor Performance Features
    18
2 Microarchitecture Overview

21
- Introduction
  21
- Intel Xscale® Microarchitecture Pipeline
  21
  - General Pipeline Characteristics
    21
    
    Pipeline Organization
    21
- Intel Xscale® Microarchitecture RISC Superpipeline
  21
- Pipelines and Pipe Stages
  22
  - ARM* V5TE Instruction Execution
    23
  - Pipeline Stalls
    23
  - Main Execution Pipeline
    23
    
    F1 / F2 (Instruction Fetch) Pipestages
    23
    
    Execute (X1) Pipestages
    24
    
    Instruction Decode (ID) Pipestage
    24
    
    Register File / Shifter (RF) Pipestage
    24
    
    D1 and D2 Pipestage
    25
    
    Execute 2 (X2) Pipestage
    25
    
    Memory Pipeline
    25
    
    Multiply/Multiply Accumulate (MAC) Pipeline
    25
    
    Write-Back (WB)
    25
    
    Behavioral Description
    26
    
    Perils of Superpipelining
    26
  - Intel® Wireless MMX™ Technology Pipeline
    27
    
    Execute Pipeline Thread
    27
    
    ID Stage
    27
    
    RF Stage
    27
- Intel® Wireless MMX™ Technology Pipeline Threads and Relation with Intel Xscale® Microarchitecture Pipeline
  27
  - X1 Stage
    28
  - X2 Stage
    28
  - XWB Stage
    28
  - Multiply Pipeline Thread
    28
    
    M1 Stage
    28
    
    M2 Stage
    28
    
    M3 Stage
    28
    
    MWB Stage
    28
    
    D1 Stage
    29
    
    D2 Stage
    29
    
    DWB Stage
    29
    
    Memory Pipeline Thread
    29
3 System Level Optimization

31
4 Intel Xscale® Microarchitecture & Intel® Wireless MMX™ Technology Optimization

49
5 High Level Language Optimization

99
- C and C++ Level Optimization
  99
  - Efficient Usage of Preloading
    99
    
    Preload Considerations
    99
    
    Preload Loop Limitations
    101
    
    Coding Technique with Preload
    102
  - Array Merging
    104
  - Cache Blocking
    106
  - Loop Interchange
    106
  - Loop Fusion
    107
  - Loop Unrolling
    107
  - Loop Conditionals
    109
  - If-Else Versus Switch Statements
    110
  - Nested If-Else and Switch Statements
    110
  - Locality in Source Code
    110
  - Choosing Data Types
    110
  - Data Alignment for Maximizing Cache Usage
    110
  - Placing Literal Pools
    112
  - Global Versus Local Variables
    112
  - Number of Parameters in Functions
    112
  - Other General Optimizations
    112
6 Power Optimization

115
- Introduction
  115
- Optimizations for Core Power
  115
  - Code Optimization for Power Consumption
    115
  - Switching Modes for Saving Power
    115
    
    Normal Mode
    115
    
    Deep Idle Mode
    116
    
    Deep-Sleep Mode
    116
    
    Idle Mode
    116
    
    Sleep Mode
    116
    
    Standby Mode
    116
  - Wireless Intel Speedstep® Technology Power Manager
    117
  - System Bus Frequency Selection
    117
    
    Fast-Bus Mode
    118
    
    Half-Turbo Mode
    118
- Optimizations for Memory and Peripheral Power
  119
  - Improved Caching and Internal Memory Usage
    119
  - SDRAM Auto Power down (APD)
    119
  - External Memory Bus Buffer Strength Registers
    119
  - Peripheral Clock Gating
    119
  - LCD Subsystem
    119
  - Voltage and Regulators
    120
  - Operating Mode Recommendations for Power Savings
    120
    
    Idle Mode
    120
    
    Normal Mode
    120
    
    Deep-Idle Mode
    121
    
    Deep-Sleep Mode
    121
    
    Sleep Mode
    121
    
    Standby Mode
    121
Performance Checklist

123
- Performance Optimization Tips
  123
- Power Optimization Guidelines
  124

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