User Manuals: Intel NIOS II FPGA Soft Processor

Manuals and User Guides for Intel NIOS II FPGA Soft Processor. We have 1 Intel NIOS II FPGA Soft Processor manual available for free PDF download: Owner Reference Manual

Intel NIOS II Owner Reference Manual

Intel NIOS II Owner Reference Manual (233 pages)

Brand: Intel | Category: Computer Hardware | Size: 2 MB

Table of Contents

Table of Contents
2
1 Introduction

8
2 Processor Architecture

14
- Processor Implementation
  15
- Register File
  16
- Arithmetic Logic Unit
  17
- Reset and Debug Signals
  21
- Exception and Interrupt Controllers
  22
  - Exception Controller
    22
  - EIC Interface
    23
  - Internal Interrupt Controller
    23
- Memory and I/O Organization
  24
  - Instruction and Data Buses
    25
  - Cache Memory
    27
  - Tightly-Coupled Memory
    29
  - Address Map
    30
  - Memory Management Unit
    30
  - Memory Protection Unit
    31
- JTAG Debug Module
  32
  - JTAG Target Connection
    32
  - Download and Execute Software
    33
  - Software Breakpoints
    33
  - Hardware Breakpoints
    33
  - Hardware Triggers
    33
  - Trace Capture
    34
- Processor Architecture Revision History
  35
3 Programming Model

36
- Operating Modes
  36
  - Supervisor Mode
    36
  - User Mode
    37
- Memory Management Unit
  37
  - Recommended Usage
    37
  - Memory Management
    38
  - Address Space and Memory Partitions
    39
  - TLB Organization
    41
  - TLB Lookups
    42
- Memory Protection Unit
  43
  - Memory Regions
    43
  - Overlapping Regions
    45
  - Enabling the MPU
    45
- Registers
  45
  - General-Purpose Registers
    45
  - Control Registers
    46
  - Shadow Register Sets
    65
- Working with the MPU
  68
  - MPU Region Read and Write Operations
    68
  - MPU Initialization
    69
  - Debugger Access
    69
- Working with ECC
  69
  - Enabling ECC
    69
  - Handling ECC Errors
    70
  - Injecting ECC Errors
    70
- Exception Processing
  74
  - Terminology
    74
  - Exception Overview
    75
  - Exception Latency
    77
  - Reset Exceptions
    77
  - Break Exceptions
    78
  - Interrupt Exceptions
    79
  - Instruction-Related Exceptions
    83
  - Other Exceptions
    88
  - Exception Processing Flow
    88
  - Determining the Cause of Interrupt and Instruction-Related Exceptions
    93
  - Handling Nested Exceptions
    94
  - Handling Nonmaskable Interrupts
    96
  - Masking and Disabling Exceptions
    96
- Memory and Peripheral Access
  98
  - Cache Memory
    99
- Instruction Set Categories
  100
  - Data Transfer Instructions
    100
  - Arithmetic and Logical Instructions
    101
  - Move Instructions
    101
  - Comparison Instructions
    102
  - Shift and Rotate Instructions
    102
  - Program Control Instructions
    103
  - Other Control Instructions
    104
  - Custom Instructions
    104
  - No-Operation Instruction
    105
  - Potential Unimplemented Instructions
    105
- Programming Model Revision History
  105
4 Instantiating the Nios II Processor

106
- Main Nios II Tab
  106
- Vectors Tab
  107
  - Reset Vector
    107
  - Exception Vector
    108
  - Fast TLB Miss Exception Vector
    108
- Caches and Memory Interfaces Tab
  109
  - Instruction Cache
    110
  - Flash Accelerator
    111
  - Data Cache
    111
  - Tightly-Coupled Memories
    111
  - Peripheral Region
    112
- Arithmetic Instructions Tab
  112
  - Arithmetic Instructions
    112
  - Arithmetic Implementation
    113
- MMU and MPU Settings Tab
  113
  - Mmu
    114
  - Mpu
    115
- JTAG Debug Tab
  115
- Advanced Features Tab
  117
  - Ecc
    117
  - Interrupt Controller Interfaces
    118
  - Shadow Register Sets
    118
  - Reset Signals
    118
  - CPU ID Control Register Value
    119
  - Generate Trace File
    119
  - Exception Checking
    119
  - Branch Prediction
    120
  - RAM Memory Protection
    120
- The Quartus Prime IP File
  120
- Instantiating the Nios II Processor Revision History
  120
5 Nios II Core Implementation Details

121
- Device Family Support
  121
- Nios II/F Core
  122
  - Overview
    122
  - Arithmetic Logic Unit
    123
  - Memory Access
    124
  - Tightly-Coupled Memory
    127
  - Memory Management Unit
    128
  - Memory Protection Unit
    128
  - Execution Pipeline
    129
  - Instruction Performance
    130
  - Exception Handling
    131
  - Ecc
    133
  - JTAG Debug Module
    134
- Nios II/S Core
  135
  - Overview
    135
  - Arithmetic Logic Unit
    135
  - Memory Access
    137
  - Tightly-Coupled Memory
    138
  - Execution Pipeline
    138
  - Instruction Performance
    139
  - Exception Handling
    140
  - JTAG Debug Module
    140
- Nios II/E Core
  140
  - Overview
    141
  - Arithmetic Logic Unit
    141
  - Memory Access
    141
  - Instruction Execution Stages
    141
  - Instruction Performance
    142
  - Exception Handling
    142
  - JTAG Debug Module
    142
- Nios II Core Implementation Details Revision History
  143
6 Nios II Processor Versions

144
- Nios II Versions
  144
- Architecture Revisions
  144
- Core Revisions
  145
  - Nios II/F Core
    145
  - Nios II/S Core
    145
  - Nios II/E Core
    145
- JTAG Debug Module Revisions
  145
- Nios II Processor Versions Revision History
  145
7 Application Binary Interface

146
- Data Types
  146
- Memory Alignment
  146
- Register Usage
  147
- Stacks
  148
  - Frame Pointer Elimination
    149
  - Call Saved Registers
    149
  - Further Examples of Stacks
    149
  - Function Prologues
    151
- Arguments and Return Values
  152
  - Arguments
    153
  - Return Values
    153
- DWARF-2 Definition
  154
- Object Files
  154
- Relocation
  154
- ABI for Linux Systems
  157
  - Linux Toolchain Relocation Information
    157
  - Linux Function Calls
    160
  - Linux Operating System Call Interface
    161
  - Linux Process Initialization
    162
  - Linux Position-Independent Code
    162
  - Linux Program Loading and Dynamic Linking
    164
  - Linux Conventions
    167
- Development Environment
  167
- Application Binary Interface Revision History
  168
8 Instruction Set Reference

169
- Word Formats
  169
  - I-Type
    169
  - R-Type
    169
  - J-Type
    170
- Instruction Opcodes
  170
- Assembler Pseudo-Instructions
  172
- Assembler Macros
  172
- Instruction Set Reference
  173
  - Add
    174
  - Addi
    175
  - And
    176
  - Andhi
    177
  - Andi
    177
  - Beq
    178
  - Bge
    178
  - Bgeu
    179
  - Bgt
    179
  - Bgtu
    180
  - Ble
    180
  - Bleu
    180
  - Blt
    181
  - Bltu
    181
  - Bne
    182
  - Break
    183
  - Bret
    184
  - Call
    184
  - Callr
    185
  - Cmpeq
    185
  - Cmpeqi
    186
  - Cmpge
    186
  - Cmpgei
    187
  - Cmpgeu
    188
  - Cmpgeui
    188
  - Cmpgt
    189
  - Cmpgti
    189
  - Cmpgtu
    189
  - Cmpgtui
    190
  - Cmple
    190
  - Cmplei
    190
  - Cmpleu
    191
  - Cmpleui
    191
  - Cmplt
    191
  - Cmplti
    192
  - Cmpltu
    193
  - Cmpltui
    193
  - Cmpne
    194
  - Cmpnei
    194
  - Custom
    195
  - DIV
    196
  - Divu
    197
  - Eret
    197
  - Flushd
    198
  - Flushda
    199
  - Flushi
    200
  - Flushp
    201
  - Initd
    201
- Initda
  203
- Initi
  204
- Jmp
  205
- Jmpi
  205
- Ldb / Ldbio
  206
- Ldbu / Ldbuio
  207
- Ldh / Ldhio
  208
- Ldhu / Ldhuio
  209
- Ldw / Ldwio
  210
- Mov
  211
- Movhi
  211
- Movi
  212
- Movia
  212
- Movui
  212
- Mul
  213
- Muli
  214
- Mulxss
  214
- Mulxsu
  215
- Mulxuu
  215
- Nextpc
  216
- Nop
  217
- Nor
  217
- Orhi
  218
- Ori
  218
- Rdctl
  219
- Rdprs
  219
- Ret
  220
- Rol
  220
- Roli
  221
- Ror
  221
- Sll
  222
- Slli
  222
- Sra
  223
- Srai
  223
- Srl
  224
- Srli
  225
- Stb / Stbio L
  225
- Sth / Sthio
  226
- Stw / Stwio
  227
- Sub
  228
- Subi
  229
- Sync
  229
- Trap
  230
- Wrctl
  230
- Wrprs
  231
- Xor
  232
- Xorhi
  232
- Xori
  233
- Instruction Set Reference Revision History
  233

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