Intel NIOS II Manuals

Manuals and User Guides for Intel NIOS II. We have 1 Intel NIOS II manual available for free PDF download: Owner Reference Manual

Intel NIOS II Owner Reference Manual (233 pages)

Brand: Intel | Category: Computer Hardware | Size: 2.25 MB

- 2
  Table of Contents
8
1 Introduction
14
2 Processor Architecture
- 15
  Processor Implementation
- 16
  Register File
- 17
  Arithmetic Logic Unit
- 21
  Reset and Debug Signals
- 22
  Exception and Interrupt Controllers
  - 22
    Exception Controller
  - 23
    EIC Interface
  - 23
    Internal Interrupt Controller
- 24
  Memory and I/O Organization
  - 25
    Instruction and Data Buses
  - 27
    Cache Memory
  - 29
    Tightly-Coupled Memory
  - 30
    Address Map
  - 30
    Memory Management Unit
  - 31
    Memory Protection Unit
- 32
  JTAG Debug Module
  - 32
    JTAG Target Connection
  - 33
    Download and Execute Software
  - 33
    Software Breakpoints
  - 33
    Hardware Breakpoints
  - 33
    Hardware Triggers
  - 34
    Trace Capture
- 35
  Processor Architecture Revision History
36
3 Programming Model
- 36
  Operating Modes
  - 36
    Supervisor Mode
  - 37
    User Mode
- 37
  Memory Management Unit
  - 37
    Recommended Usage
  - 38
    Memory Management
  - 39
    Address Space and Memory Partitions
  - 41
    TLB Organization
  - 42
    TLB Lookups
- 43
  Memory Protection Unit
  - 43
    Memory Regions
  - 45
    Overlapping Regions
  - 45
    Enabling the MPU
- 45
  Registers
  - 45
    General-Purpose Registers
  - 46
    Control Registers
  - 65
    Shadow Register Sets
- 68
  Working with the MPU
  - 68
    MPU Region Read and Write Operations
  - 69
    MPU Initialization
  - 69
    Debugger Access
- 69
  Working with ECC
  - 69
    Enabling ECC
  - 70
    Handling ECC Errors
  - 70
    Injecting ECC Errors
- 74
  Exception Processing
  - 74
    Terminology
  - 75
    Exception Overview
  - 77
    Exception Latency
  - 77
    Reset Exceptions
  - 78
    Break Exceptions
  - 79
    Interrupt Exceptions
  - 83
    Instruction-Related Exceptions
  - 88
    Other Exceptions
  - 88
    Exception Processing Flow
  - 93
    Determining the Cause of Interrupt and Instruction-Related Exceptions
  - 94
    Handling Nested Exceptions
  - 96
    Handling Nonmaskable Interrupts
  - 96
    Masking and Disabling Exceptions
- 98
  Memory and Peripheral Access
  - 99
    Cache Memory
- 100
  Instruction Set Categories
  - 100
    Data Transfer Instructions
  - 101
    Arithmetic and Logical Instructions
  - 101
    Move Instructions
  - 102
    Comparison Instructions
  - 102
    Shift and Rotate Instructions
  - 103
    Program Control Instructions
  - 104
    Other Control Instructions
  - 104
    Custom Instructions
  - 105
    No-Operation Instruction
  - 105
    Potential Unimplemented Instructions
- 105
  Programming Model Revision History
106
4 Instantiating the Nios II Processor
- 106
  Main Nios II Tab
- 107
  Vectors Tab
  - 107
    Reset Vector
  - 108
    Exception Vector
  - 108
    Fast TLB Miss Exception Vector
- 109
  Caches and Memory Interfaces Tab
  - 110
    Instruction Cache
  - 111
    Flash Accelerator
  - 111
    Data Cache
  - 111
    Tightly-Coupled Memories
  - 112
    Peripheral Region
- 112
  Arithmetic Instructions Tab
  - 112
    Arithmetic Instructions
  - 113
    Arithmetic Implementation
- 113
  MMU and MPU Settings Tab
  - 114
    Mmu
  - 115
    Mpu
- 115
  JTAG Debug Tab
- 117
  Advanced Features Tab
  - 117
    Ecc
  - 118
    Interrupt Controller Interfaces
  - 118
    Shadow Register Sets
  - 118
    Reset Signals
  - 119
    CPU ID Control Register Value
  - 119
    Generate Trace File
  - 119
    Exception Checking
  - 120
    Branch Prediction
  - 120
    RAM Memory Protection
- 120
  The Quartus Prime IP File
- 120
  Instantiating the Nios II Processor Revision History
121
5 Nios II Core Implementation Details
- 121
  Device Family Support
- 122
  Nios II/F Core
  - 122
    Overview
  - 123
    Arithmetic Logic Unit
  - 124
    Memory Access
  - 127
    Tightly-Coupled Memory
  - 128
    Memory Management Unit
  - 128
    Memory Protection Unit
  - 129
    Execution Pipeline
  - 130
    Instruction Performance
  - 131
    Exception Handling
  - 133
    Ecc
  - 134
    JTAG Debug Module
- 135
  Nios II/S Core
  - 135
    Overview
  - 135
    Arithmetic Logic Unit
  - 137
    Memory Access
  - 138
    Tightly-Coupled Memory
  - 138
    Execution Pipeline
  - 139
    Instruction Performance
  - 140
    Exception Handling
  - 140
    JTAG Debug Module
- 140
  Nios II/E Core
  - 141
    Overview
  - 141
    Arithmetic Logic Unit
  - 141
    Memory Access
  - 141
    Instruction Execution Stages
  - 142
    Instruction Performance
  - 142
    Exception Handling
  - 142
    JTAG Debug Module
- 143
  Nios II Core Implementation Details Revision History
144
6 Nios II Processor Versions
- 144
  Nios II Versions
- 144
  Architecture Revisions
- 145
  Core Revisions
  - 145
    Nios II/F Core
  - 145
    Nios II/S Core
  - 145
    Nios II/E Core
- 145
  JTAG Debug Module Revisions
- 145
  Nios II Processor Versions Revision History
146
7 Application Binary Interface
- 146
  Data Types
- 146
  Memory Alignment
- 147
  Register Usage
- 148
  Stacks
  - 149
    Frame Pointer Elimination
  - 149
    Call Saved Registers
  - 149
    Further Examples of Stacks
  - 151
    Function Prologues
- 152
  Arguments and Return Values
  - 153
    Arguments
  - 153
    Return Values
- 154
  DWARF-2 Definition
- 154
  Object Files
- 154
  Relocation
- 157
  ABI for Linux Systems
  - 157
    Linux Toolchain Relocation Information
  - 160
    Linux Function Calls
  - 161
    Linux Operating System Call Interface
  - 162
    Linux Process Initialization
  - 162
    Linux Position-Independent Code
  - 164
    Linux Program Loading and Dynamic Linking
  - 167
    Linux Conventions
- 167
  Development Environment
- 168
  Application Binary Interface Revision History
169
8 Instruction Set Reference
- 169
  Word Formats
  - 169
    I-Type
  - 169
    R-Type
  - 170
    J-Type
- 170
  Instruction Opcodes
- 172
  Assembler Pseudo-Instructions
- 172
  Assembler Macros
- 173
  Instruction Set Reference
  - 174
    Add
  - 175
    Addi
  - 176
    And
  - 177
    Andhi
  - 177
    Andi
  - 178
    Beq
  - 178
    Bge
  - 179
    Bgeu
  - 179
    Bgt
  - 180
    Bgtu
  - 180
    Ble
  - 180
    Bleu
  - 181
    Blt
  - 181
    Bltu
  - 182
    Bne
  - 183
    Break
  - 184
    Bret
  - 184
    Call
  - 185
    Callr
  - 185
    Cmpeq
  - 186
    Cmpeqi
  - 186
    Cmpge
  - 187
    Cmpgei
  - 188
    Cmpgeu
  - 188
    Cmpgeui
  - 189
    Cmpgt
  - 189
    Cmpgti
  - 189
    Cmpgtu
  - 190
    Cmpgtui
  - 190
    Cmple
  - 190
    Cmplei
  - 191
    Cmpleu
  - 191
    Cmpleui
  - 191
    Cmplt
  - 192
    Cmplti
  - 193
    Cmpltu
  - 193
    Cmpltui
  - 194
    Cmpne
  - 194
    Cmpnei
  - 195
    Custom
  - 196
    DIV
  - 197
    Divu
  - 197
    Eret
  - 198
    Flushd
  - 199
    Flushda
  - 200
    Flushi
  - 201
    Flushp
  - 201
    Initd
- 203
  Initda
- 204
  Initi
- 205
  Jmp
- 205
  Jmpi
- 206
  Ldb / Ldbio
- 207
  Ldbu / Ldbuio
- 208
  Ldh / Ldhio
- 209
  Ldhu / Ldhuio
- 210
  Ldw / Ldwio
- 211
  Mov
- 211
  Movhi
- 212
  Movi
- 212
  Movia
- 212
  Movui
- 213
  Mul
- 214
  Muli
- 214
  Mulxss
- 215
  Mulxsu
- 215
  Mulxuu
- 216
  Nextpc
- 217
  Nop
- 217
  Nor
- 218
  Orhi
- 218
  Ori
- 219
  Rdctl
- 219
  Rdprs
- 220
  Ret
- 220
  Rol
- 221
  Roli
- 221
  Ror
- 222
  Sll
- 222
  Slli
- 223
  Sra
- 223
  Srai
- 224
  Srl
- 225
  Srli
- 225
  Stb / Stbio L
- 226
  Sth / Sthio
- 227
  Stw / Stwio
- 228
  Sub
- 229
  Subi
- 229
  Sync
- 230
  Trap
- 230
  Wrctl
- 231
  Wrprs
- 232
  Xor
- 232
  Xorhi
- 233
  Xori
233
Instruction Set Reference Revision History

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Intel NIOS II Manuals

Manuals and User Guides for Intel NIOS II. We have 1 Intel NIOS II manual available for free PDF download: Owner Reference Manual

Intel NIOS II Owner Reference Manual (233 pages)

Table of Contents

8 1 Introduction

14 2 Processor Architecture

36 3 Programming Model

106 4 Instantiating the Nios II Processor

121 5 Nios II Core Implementation Details

144 6 Nios II Processor Versions

146 7 Application Binary Interface

169 8 Instruction Set Reference

233 Instruction Set Reference Revision History

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Intel Categories

8
1 Introduction

14
2 Processor Architecture

36
3 Programming Model

106
4 Instantiating the Nios II Processor

121
5 Nios II Core Implementation Details

144
6 Nios II Processor Versions

146
7 Application Binary Interface

169
8 Instruction Set Reference

233
Instruction Set Reference Revision History