Bit Bus Read/Write Device Interface - Intel 80C186XL User Manual

BUS INTERFACE UNIT
Most memory and peripheral devices latch data on the rising edge of the write strobe. Address,
chip-select and data must be valid (set up) prior to the rising edge of WR. T
fine the minimum data setup requirements. The value calculated by their respective equations
must be greater than the device requirements. To increase the calculated value, insert wait states.
LA15:1
RD
LA0
WR
BHE
LCS
Figure 3-22. 16-Bit Bus Read/Write Device Interface
3-24
A0:14
OE
I/O1:8
WE
CS1
A0:14
OE
I/O1:8
WE
CS1
, T and T de-
AW CW DW
AD7:0
AD15:8
A1106-0A