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2.7
BIST interface
ARM DDI 0275D
ATPG testing can only test out the interface between the ETB11 RAM and the ETB11.
It is unable to find faults in the actual RAM. A Built-In Self Test (BIST) interface is
required that fully tests the RAM.
ATPG vectors are created using Synopsys TetraMax. These enable the shadow logic
around the ETB11 RAM to be tested provided that the TetraMax has access to a model
of the RAM used. Greater than 99% stuck-at fault coverage can be achieved.
A block diagram of the BIST interface is shown in Figure 2-4.
Etb11Int
The MTESTON signal gives an external BIST controller access to the inputs and
outputs of the ETB11 RAM. It is not possible for the ETB11 to operate in functional
mode when the BIST is testing the RAM. When MTESTON is HIGH do not:
•
set the TraceCaptEn bit
•
write to the ETB11 RAM
•
read from the ETB11 RAM.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
ETB11 RAM
A
A
MBISTADDR
DIN
DIN
MBISTDIN
CS
CS
MBISTCE
WE
WE
MBISTWE
MTESTON
CLK
CLK
Figure 2-4 BIST interface block diagram
Functional Description
DOUT
MBISTDOUT
2-11
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