Figure 4-3 Onesegx32 Interface - ARM ARM966E-S Technical Reference Manual

Tightly-coupled SRAM
4.4.1 Example SRAM interfaces
4-8
and generate the SRAM specific ChipSelect, WriteEnable, and
IRamIF.v DRamIF.v
ByteWrite signals. Your own library RAMs are instantiated inside
DataRAM.v .
The example wrapper supplied by ARM contains three RAM interface examples. All of
the interface modifications are done in the
I-SRAM and D-SRAM respectively. The example SRAM interfaces are:
• ONESEGX32
• FOURSEGX32 on page 4-9
• FOURSEGX8 on page 4-10.
Note
The examples shown here are for 32KByte I-SRAM (8K words x 4bytes). The interface
for D-SRAM is identical.
ONESEGX32
Figure 4-3 shows the simplest interface I-SRAM. To use this, the SRAM must consist
of a single word-wide RAM that has byte-write control.
Only single ChipSelect and WriteEnable signals are required.
Copyright © 2000 ARM Limited. All rights reserved.
and the
IRamIF.v
ByteWrite[3:0]
ICtrl.v
RamAddr[12:0]
WriteEnable
IRamIF.v
ChipSelect

Figure 4-3 ONESEGX32 interface

and
InstrRAM.v
blocks for the
DRamIF.v
8Kx32
IRData[31:0]
ARM DDI 0186A