A3.2 Asynchronous Interface - ARM Cortex-A76 Core Technical Reference Manual

A3.2 Asynchronous interface
Your implementation can include an optional asynchronous interface between the core and the DSU top
level.
See the Arm
100798_0300_00_en
DynamIQ Shared Unit Technical Reference Manual for more information.
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A3 Clocks, resets, and input synchronization

A3.2 Asynchronous interface

A3-43