Figure 1-5 Example Reset Circuit Logic - ARM DS-5 Manual

1.2.3 Example reset circuits
The diagram shows a typical reset circuit logic for the ARM reset signals and the DSTREAM reset
signals.
Related references
1.2.1 ARM reset signals on page 1-16.
1.2.2 DSTREAM reset signals on page 1-16.
ARM 100956_0527_00_en
VDD
nTRST
VDD
nSRST
Manual
reset
Copyright © 2010–2012, 2015–2017 ARM Limited or its affiliates. All rights reserved.
Non-Confidential
1 ARM DSTREAM System Design Guidelines
VDD
RST
10K
TAP RESET
Open-drain
reset devices
e.g. STM1001
VDD
RST
10K
SYSTEM RESET
100R
100nF
Gnd Gnd

Figure 1-5 Example reset circuit logic

1.2 Reset signals
TRST
ARM
Processor
RESET
To other
logic
1-17