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2.11
AHB transfers
2.11.1
Read transfer
ARM DDI 0275D
This section describes:
•
Read transfer
•
Write transfer on page 2-22.
Two types of read transfer are described:
•
Asynchronous HCLK and CLK
•
Synchronous HCLK and CLK on page 2-22.
Asynchronous HCLK and CLK
When HSEL goes HIGH, this indicates that an AHB transfer involving the ETB11
AHB interface has started. On the same cycle that HSEL is asserted, the type of transfer
and the address of the transfer are specified on HWRITE and HADDR respectively.
HReq goes HIGH after HSEL goes HIGH, indicating the start of the synchronization
period between the HCLK and CLK domain if the SBYPASS signal is LOW. HReq is
registered twice in the CLK domain to form CReq. When CReq goes HIGH, the
address value on HADDRReg, the registered version of HADDR that remains valid
until HReq goes LOW, is valid. The CS and CRegRead signals that control read access
of the ETB11 RAM and the ETB11 registers go HIGH for one cycle after CReq goes
HIGH.
Data is returned from the ETB11 RAM or the ETB11 registers and registered into
CData. CAck goes HIGH to indicate that the read value has been retrieved.
CAck is registered twice in the HCLK domain to form HAck. After HAck goes HIGH,
HRDATAMEM gets the value of MuxedData (a multiplexed version of the data
returned from RAM, registers, and CData) and HREADYMEM goes HIGH indicating
to the AHB bus master that the data on HRDATAMEM is valid.
HReq then goes LOW, indicating that the AHB transfer has finished. This causes CAck
to go LOW one cycle after CReq goes LOW.
Finally, HAck goes LOW, finishing the read cycle.
How the CReq, CAck, and HAck signals are produced is shown in Figure 2-8 on
page 2-20.
Copyright © 2002, 2003 ARM Limited. All rights reserved.
Functional Description
2-19
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