B4.10 Icc_Sre_El2, Interrupt Controller System Register Enable Register, El2 - ARM Cortex-A76 Core Technical Reference Manual

B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2
ICC_SRE_EL2 controls whether the system register interface or the memory-mapped interface to the
GIC CPU interface is used for EL2.
Bit field descriptions
ICC_SRE_EL2 is a 32-bit register and is part of:
• The GIC system registers functional group.
• The Virtualization registers functional group.
• The GIC control registers functional group.
31
RES
RES0, [31:4]
Enable, [3]
DIB, [2]
DFB, [1]
SRE, [0]
100798_0300_00_en
0
Reserved, .
RES0
Enables lower Exception level access to ICC_SRE_EL1. The value is:
Non-secure EL1 accesses to ICC_SRE_EL1 do not trap to EL2.
0x1
This bit is RAO/WI.
Disable IRQ bypass. The possible values are:
IRQ bypass enabled.
0x0
IRQ bypass disabled.
0x1
This bit is an alias of ICC_SRE_EL3.DIB
Disable FIQ bypass. The possible values are:
FIQ bypass enabled.
0x0
FIQ bypass disabled.
0x1
This bit is an alias of ICC_SRE_EL3.DFB
System Register Enable. The value is:
The System register interface for the current Security state is enabled.
0x1
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B4.10 ICC_SRE_EL2, Interrupt Controller System Register Enable register, EL2

Figure B4-6 ICC_SRE_EL2 bit assignments
reserved.
Non-Confidential
B4 GIC registers
4 3 2 1 0
SRE
DFB
DIB
Enable
B4-324