Dac Channel2 12-Bit Right Aligned Data Holding Register; Dac Channel2 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L2); Dac Channel2 8-Bit Right-Aligned Data Holding Register - ST STM32F207 Series Reference Manual

RM0033
11.5.6

DAC channel2 12-bit right aligned data holding register

(DAC_DHR12R2)
Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved, must be kept at reset value.
Bits 11:0 DACC2DHR[11:0]: DAC channel2 12-bit right-aligned data
These bits are written by software which specifies 12-bit data for DAC channel2.
11.5.7

DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2)

Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
Bits 3:0 Reserved, must be kept at reset value.
11.5.8

DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2)
Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
27 26 25
11 10 9
rw rw rw
27 26 25
11 10 9
DACC2DHR[11:0]
rw rw rw rw
These bits are written by software which specify 12-bit data for DAC channel2.
27 26 25
11 10 9
Reserved
These bits are written by software which specifies 8-bit data for DAC channel2.
24 23 22
Reserved
8 7 6
DACC2DHR[11:0]
rw rw rw
24 23 22
Reserved
8 7 6
rw rw rw
24 23 22
Reserved
8 7 6
rw rw
RM0033 Rev 9
Digital-to-analog converter (DAC)
21 20 19 18
5 4 3 2
rw rw rw rw
21 20 19 18
5 4 3 2
Reserved
rw rw
21 20 19 18
5 4 3 2
DACC2DHR[7:0]
rw rw rw rw
17 16
1 0
rw rw
17 16
1 0
17 16
1 0
rw rw
273/1381
277