Dac Channel2 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L2); Dac Channel2 8-Bit Right-Aligned Data Holding Register; (Dac_Dhr8R2) - ST STM32F40 Series Reference Manual

RM0090
12.5.7

DAC channel2 12-bit left aligned data holding register

(DAC_DHR12L2)

Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
rw rw rw
Bits 31:16 Reserved, must be kept at reset value.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit left-aligned data
Bits 3:0 Reserved, must be kept at reset value.
12.5.8

DAC channel2 8-bit right-aligned data holding register

(DAC_DHR8R2)

Address offset: 0x1C
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Bits 31:8 Reserved, must be kept at reset value.
Bits 7:0 DACC2DHR[7:0]: DAC channel2 8-bit right-aligned data
12.5.9 Dual DAC 12-bit right-aligned data holding register
(DAC_DHR12RD)
Address offset: 0x20
Reset value: 0x0000 0000
31 30 29 28
Reserved
15 14 13 12
Reserved
27 26 25
11 10 9
DACC2DHR[11:0]
rw rw rw rw
These bits are written by software which specify 12-bit data for DAC channel2.
27 26 25
11 10 9
Reserved
These bits are written by software which specifies 8-bit data for DAC channel2.
27 26 25
rw rw rw
11 10 9
rw rw rw
Doc ID 018909 Rev 4
Digital-to-analog converter (DAC)
24 23 22 21
Reserved
8 7 6 5
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
rw rw rw
24 23 22 21
DACC2DHR[11:0]
rw rw rw rw
8 7 6 5
DACC1DHR[11:0]
rw rw rw rw
20 19 18 17
4 3 2
Reserved
rw
20 19 18 17
4 3 2
DACC2DHR[7:0]
rw rw rw rw
20 19 18 17
rw rw rw rw
4 3 2
rw rw rw rw
16
1 0
16
1 0
rw
16
rw
1 0
rw
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