Dac Channel2 12-Bit Right Aligned Data Holding Register; (Dac_Dhr12R2); Dac Channel2 12-Bit Left Aligned Data Holding Register; (Dac_Dhr12L2) - ST STM32F102 Series Reference Manual

RM0008
11.5.6

DAC channel2 12-bit Right aligned Data Holding Register

(DAC_DHR12R2)

Address offset: 0x14
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
Reserved
Bits 31:12 Reserved.
DACC2DHR[11:0]: DAC channel2 12-bit Right aligned data
Bits 11:0
These bits are written by software which specify 12-bit data for DAC channel2.
11.5.7

DAC channel2 12-bit Left aligned Data Holding Register

(DAC_DHR12L2)

Address offset: 0x18
Reset value: 0x0000 0000
31 30 29 28
15 14 13 12
rw rw rw
Bits 31:16 Reserved.
Bits 15:4 DACC2DHR[11:0]: DAC channel2 12-bit Left aligned data
These bits are written by software which specify 12-bit data for DAC channel2.
Bits 3:0 Reserved.
27 26 25
11 10 9
rw rw rw
27 26 25
11 10 9
DACC2DHR[11:0]
rw rw rw rw
Digital-to-analog converter (DAC)
24 23 22 21
Reserved
8 7 6 5
DACC2DHR[11:0]
rw rw rw rw
24 23 22 21
Reserved
8 7 6 5
rw rw rw rw
20 19 18 17
4 3 2 1
rw rw rw rw
20 19 18 17
4 3 2 1
Reserved
rw
16
0
rw
16
0
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