Table of Contents
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Chapter 1
Overview
This chapter provides an overview of the MPC750 microprocessor features, including a
block diagram showing the major functional components. It provides information about
how the MPC750 implementation complies with the PowerPCTM architecture definition.
1.1 MPC750 Microprocessor Overview
This section describes the features and general operation of the MPC750 and provides a
block diagram showing major functional units. The MPC750 is an implementation of the
PowerPC microprocessor family of reduced instruction set computer (RISC)
microprocessors. The MPC750 implements the 32-bit portion of the PowerPC architecture,
which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and
floating-point data types of 32 and 64 bits. The MPC750 is a superscalar processor that can
complete two instructions simultaneously. It incorporates the following six execution units:
•
Floating-point unit (FPU)
•
Branch processing unit (BPU)
•
System register unit (SRU)
•
Load/store unit (LSU)
•
Two integer units (IUs): lUI executes all integer instructions. IU2 executes all
integer instructions except multiply and divide instructions.
The ability to execute several instructions in parallel and the use of simple instructions with
rapid execution times yield high efficiency and throughput for MPC750-based systems.
Most integer instructions execute in one clock cycle. The FPU is pipe lined, the tasks it
performs are broken into subtasks, implemented as three successive stages. Typically, a
floating-point instruction can occupy only one of the three stages at a time, freeing the
previous stage to work on the next floating-point instruction. Thus, three single-precision
floating-point instructions can be in the FPU execute stage at a time. Double-precision add
instructions have a three-cycle latency; double-precision multiply and multiply-add
instructions have a four-cycle latency.
Chapter 1. Overview
1-1
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