Core Architecture Overview; Core Block Diagram - Motorola DSP56800 Manual

Chapter 2

Core Architecture Overview

The DSP56800 core architecture is a 16-bit multiple-bus processor designed for efficient real-time digital
signal processing and general purpose computing. The architecture is designed as a standard
programmable core from which various DSP integrated circuit family members can be designed with
different on-chip and off-chip memory sizes and on-chip peripheral requirements. This chapter presents
the overall core architecture and the general programming model. More detailed information on the data
ALU, AGU, program controller, and JTAG/OnCE blocks within the architecture are found in later
chapters.
2.1

Core Block Diagram

The DSP56800 core is composed of functional units that operate in parallel to increase the throughput of
the machine. The program controller, AGU, and data ALU each contain their own register set and control
logic, so each may operate independently and in parallel with the other two. Likewise, each functional unit
interfaces with other units, with memory, and with memory-mapped peripherals over the core's internal
address and data buses. The architecture is pipelined to take advantage of the parallel units and
significantly decrease the execution time of each instruction.
For example, it is possible for the data ALU to perform a multiplication in a first instruction, for the AGU
to generate up to two addresses for a second instruction, and for the program controller to be fetching a
third instruction. In a similar manner, it is possible for the bit-manipulation unit to perform an operation of
the third instruction described above in place of the multiplication in the data ALU.
The major components of the core are the following:
• Data ALU
• AGU
• Program controller and hardware looping unit
• Bus and bit-manipulation unit
• OnCE debug port
• Address buses
• Data buses
Figure 2-1 on page 2-2 shows a block diagram of the CPU architecture.
Core Architecture Overview 2-1