Standard Pcs Parameters - Intel Arria 10 User Manual

Table 29. KR-FEC Parameters
Parameter
Enable RX KR-FEC
error marking
Error marking type
Enable KR-FEC TX
error insertion
KR-FEC TX error
insertion spacing
Enable tx_enh_frame
port
Enable rx_enh_frame
port
Enable
rx_enh_frame_diag_st
atus port
Related Information
• Arria 10 Enhanced PCS Architecture
• Using the "Basic (Enhanced PCS)" and "Basic with KR FEC" Configurations of
Enhanced PCS
• Interlaken
• 10GBASE-KR PHY IP Core
• Enhanced PCS Ports
• 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants
page 124

2.4.5. Standard PCS Parameters

This section provides descriptions of the parameters that you can specify to customize
the Standard PCS.
For specific information about configuring the Standard PCS for these protocols, refer
to the sections of this user guide that describe support for these protocols.
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Intel Arria 10 Transceiver PHY User Guide
62
Range
On/Off When you turn on this option, the decoder asserts both sync bits
(2'b11) when it detects an uncorrectable error. This feature
increases the latency through the KR-FEC decoder.
10G, 40G Specifies the error marking type (10G or 40G).
On/Off Enables the error insertion feature of the KR-FEC encoder. This
feature allows you to insert errors by corrupting data starting a bit
0 of the current word.
User Input (1 bit to 15 Specifies the spacing of the KR-FEC TX error insertion.
bit)
On/Off Enables the tx_enh_frame port.
On/Off Enables the rx_enh_frame port.
On/Off Enables the rx_enh_frame_diag_status port.
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on page 94
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2. Implementing Protocols in Arria 10 Transceivers
Description
on page 461
UG-01143 | 2018.06.15
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