Fpll Ports For Pipe - Intel Arria 10 User Manual

Signal Name
pipe_tx_deemph
pipe_tx_sync_hdr
pipe_tx_blk_start
pipe_tx_data_valid
pipe_rx_sync_hdr
pipe_rx_blk_start
pipe_rx_data_valid
Refer to section 6.6 of Intel PHY Interface for PCI Express (PIPE) Architecture for more
information.
Related Information
• PHY IP Core for PCIe (PIPE) Link Equalization for Gen3 Data Rate
• Intel PHY Interface for PCI Express (PIPE) Architecture
• Bit Mappings When the Simplified Interface is Disabled
• Using the Arria 10 Transceiver Native PHY IP Core

2.7.9. fPLL Ports for PIPE

Table 192. fPLL Ports for PIPE
This section contains the recommended settings for this protocol. Refer to Using the Arria 10 Transceiver
Native PHY IP Core for the full range of parameter settings.
Port
Pll_powerdown
Pll_reflck0
tx_serial_clk
® ®
Intel Arria 10 Transceiver PHY User Guide
264
Gen1 (TX Byte Gen1 (TX Byte
Serializer and RX Serializer and RX Byte
Byte Deserializer Deserializer in X2
disabled) mode), Gen2 (TX Byte
Serializer and RX Byte
Deserializer in X2
tx_parallel_data[52
N/A
]
N/A
N/A
N/A
N/A
N/A
N/A
Direction Clock Domain
Input Asynchronous
Input N/A
Output N/A
2. Implementing Protocols in Arria 10 Transceivers
mode)
N/A
tx_parallel_data[55:54]
N/A
tx_parallel_data[56]
N/A
tx_parallel_data[60]
N/A
rx_parallel_data[71:70]
N/A
rx_parallel_data[72]
N/A
rx_parallel_data[76]
on page 263
on page 45
Description
Resets the PLL when asserted high. Needs to be connected
to a dynamically controlled signal (the Transceiver PHY
Reset Controller
pll_powerdown
FPGA IP).
Reference clock input port 0. There are five reference clock
input ports. The number of reference clock ports available
depends on the Number of PLL reference clocks parameter.
High speed serial clock output port for GX channels.
Represents the x1 clock network.
For Gen1x1, Gen2x1, connect the output from this port to
the input of the native PHY IP.
tx_serial_clk
For Gen1x2, x4, x8, use the
port to connect to the Native PHY IP.
For Gen2x2, x4, x8, use the
port to connect to the Native PHY IP.
For Gen3x1, connect the output from this port to one of
the two input ports on the native PHY IP.
tx_serial_clk
For Gen3x2, x4, x8, connect the output from this port to
the Auxiliary Master CGB clock input port of the ATX PLL IP.
UG-01143 | 2018.06.15
Gen3
N/A
on page 274
output if using this Intel
output
tx_bonding_clocks
output
tx_bonding_clocks
continued...